Senior DFT Engineer — SoC Test & Validation

Avensys Consulting; Kuala Lumpur; On-site; MYR 120,000 - 180,000; Full time

Job summary

Avensys is seeking a skilled DFT Engineer to design and implement DFT solutions for complex SoC/ASIC designs, working with Physical Design, Verification and other engineering teams. You will develop DFT architectures, generate test patterns and support silicon bring-up to ensure high test coverage and product quality.

The ideal candidate has 4+ years of hands-on DFT/VLSI experience, expertise in Scan Architecture, ATPG, and familiarity with Synopsys DFT Compiler.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics or a related field.
• 4+ years of hands-on experience in DFT / VLSI design.
• Strong practical experience with SoC/ASIC DFT implementation.
• Experience working with full-chip or block-level DFT flows.
• Hands-on experience with Synopsys DFT Compiler.
• Strong experience with Scan Architecture and Scan Insertion.
• Experience with ATPG and fault modeling.
• Good understanding of test compression techniques.
• Experience with Boundary Scan (JTAG) implementation.
• Good understanding of digital design fundamentals.
• Solid understanding of timing and physical design constraints related to DFT.
• Experience supporting DFT activities through pre-silicon and post-silicon validation.
• Experience with Tcl and/or Python scripting is an added advantage.
• Exposure to advanced process nodes is a plus.

Responsibilities

• Design and implement DFT architectures for complex SoC/ASIC designs, including: Scan insertion
• MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test)
• Perform ATPG and analyze test coverage
• Implement and optimize test compression techniques to improve efficiency
• Debug DFT-related issues during pre-silicon and post-silicon stages
• Support silicon bring-up and validation activities
• Work with Design Verification and Physical Design teams for DFT closure
• Ensure DFT implementations comply with methodologies and quality standards
• Analyze test coverage reports to identify gaps and improvements
• Troubleshoot DFT-related production test issues
• Support production test readiness and DFT process improvements

Skills

DFT architecture

Scan insertion

MBIST

LBIST

ATPG

test compression

JTAG

timing constraints

Scripting (Tcl/Python)

Education

Electrical Engineering

Electronics Engineering

VLSI

Microelectronics

Tools

Synopsys DFT Compiler

Job description

Avensys is seeking a skilled DFT Engineer to design and implement DFT solutions for complex SoC/ASIC designs, working with Physical Design, Verification and other engineering teams. You will develop DFT architectures, generate test patterns and support silicon bring-up to ensure high test coverage and product quality.

The ideal candidate has 4+ years of hands-on DFT/VLSI experience, expertise in Scan Architecture, ATPG, and familiarity with Synopsys DFT Compiler.