SoC DFX Scan Engineer

Infinecs Systems Pvt. Ltd.; Malaysia; On-site; MYR 90,000 - 130,000; Full time

Job summary

Infinecs Systems Pvt. Ltd. is seeking an experienced DFT/Scan engineer to lead tile- and chip-level scan strategies, ATPG, and verification.

You will collaborate with test engineers on ATE pattern bring-up, debugging, and failure analysis to ensure robust test coverage across SoC designs. The role requires a strong background in DFT/Scan, SSN and burn-in scan, and hands-on scripting in Perl/Python/Tcl. A minimum of five years in semiconductor or related fields is expected, with excellent

Qualifications

• Bachelor's Degree in Engineering, Quality Management, Science or related disciplines.
• Minimum 5 years of experience in DFT, scan insertion, ATPG, scan verification, or silicon debug within semiconductor or SoC design environments.
• Solid background on process, device or ASIC design.
• Strong technical background in scan, SSN and burnin scan.
• Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a plus.
• Good knowledge on DFT Scan/BIST will be a plus.
• Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.
• Good communication skills and self-driven, willing to learn/share.

Responsibilities

• Study and implement cutting-edge test strategies.
• Responsible for tile level scan insertion, ATPG and scan quality check.
• Responsible for tile level scan DRC check, non-scan analysis and test coverage improvement.
• Responsible for chip level scan test patterns/vectors generation and verification.
• Co-work with test engineers on Scan ATE patterns bring-up, debugging and failure analysis.

Skills

DFT & Scan Insertion

ATPG

Scan Verification

Silicon Debug

Test Coverage

Communication

Education

Bachelor's Degree in Engineering/Quality Management/Science

Tools

Perl

Python

Tcl

Job description

Responsibilities

• Cutting-edge test strategies study and implementation.


• Responsible for tile level scan insertion, ATPG and scan quality check.


• Responsible for tile level scan drc check, non-scan analysis and test coverage improvement


• Responsible for chip level scan test patterns/vectors generation and verification.


• Co-work with test engineers on Scan ATE patterns bring-up, debugging and failure analysis.

Requirements

• Bachelor's Degree in Engineering, Quality Management, Science or related disciplines.


• Minimum 5 years of experience in DFT, scan insertion, ATPG, scan verification, or silicon debug within semiconductor or SoC design environments.


• Solid background on process, device or ASIC design.


• Strong technical background in scan, SSN and burnin scan.


• Good knowledge on JTAG 1149.1, 1500 and 1687 protocols will be a plus.


• Good knowledge on DFT Scan/BIST will be a plus.


• Strong programming and scripting skills in Perl, Tcl or Python will be a strong plus.


• Good communication skills and self-driven, willing to learn/share.