Senior/Lead Physical Design Engineer

T-FOOTPRINT; Bayan Lepas; On-site; MYR 180,000 - 300,000; Full time

Job summary

T-FOOTPRINT in Bayan Lepas, Penang is seeking a Senior/Lead Physical Design Engineer with 5+ years of ASIC/SoC experience to drive next-generation GPU/AI accelerator projects. You will lead physical implementation from floorplanning to sign-off using advanced-node technologies.

You will collaborate with RTL, architecture and verification teams, optimize timing, power and area, and ensure on-time tape-out while applying best practices in PPA, SI/EM, DRC/LVS, and sign-off processes.

Qualifications

• 5+ years hands-on ASIC/SoC physical design experience.
• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• Proficiency in Unix/Linux environments.
• Experience with Fusion Compiler, ICC2, PrimeTime or Calibre.
• Strong teamwork and communication skills.

Responsibilities

• Execute full-chip or block-level physical design for GPU/AI accelerator SoCs, from floorplanning to sign-off, optimizing for timing, power, and area targets.
• Perform place & route, CTS, routing, optimization, timing closure, and physical sign-off (SI, IR/EM, DRC/LVS).
• Debug and resolve congestion, timing, and power integrity issues, including ECO support.
• Collaborate with RTL, architecture, and verification teams to improve physical implementation quality.
• Track execution progress and support activities to ensure on-time tape-out.
• Learn and apply best practices in advanced-node physical design.

Education

Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering

Tools

Fusion Compiler

ICC2

PrimeTime

Calibre

Job description

We are hiring a Senior / Lead Physical Design Engineer with 5+ years of experience to join our team in Bayan Lepas, Penang. You will work on next-generation GPU/AI accelerator SoCs, tackling complex design challenges and driving high-quality implementation using advanced-node technologies.

Key Responsibilities

• Execute full-chip or block-level physical design for GPU/AI accelerator SoCs, from floorplanning to sign-off, optimizing for timing, power, and area (PPA) targets.
• Perform place & route, CTS, routing, optimization, timing closure, and physical sign-off (SI, IR/EM, DRC/LVS).
• Debug and resolve congestion, timing, and power integrity issues, including ECO support.
• Collaborate with RTL, architecture, and verification teams to improve physical implementation quality.
• Track execution progress and support activities to ensure on-time tape-out.
• Learn and apply best practices in advanced-node physical design.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, or any related field
• 5+ years of hands-on experience in ASIC/SoC Physical Design.
• Proficiency in Unix/Linux environments.
• Experience with EDA tools such as Fusion Compiler, ICC2, PrimeTime, or Calibre
• Good teamwork and communication skills are mandatory