Lead Physical Design Engineer

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bayan Lepas; On-site; MYR 210,000 - 330,000; Full time

Job summary

SignOff Semiconductors Pvt. Ltd. is seeking a Lead Physical Design Engineer in Bayan Lepas to drive the PD flow for complex sub-systems from RTL to GDSII.You will lead floorplanning, CTS, routing, signoff and ECO cycles while coordinating with block PD teams.

The role requires 10+ years in ASIC/SoC PD, strong tool expertise (Innovus, Tempus, Voltus, RedHawk, Calibre) and proven leadership. Proficiency in low-power methods and multi-voltage designs is essential.

Qualifications

• 10+ years of ASIC/SOC Physical Design experience with at least 1+ year in a lead role.
• Strong expertise in industry standard PD tools (Innovus, Tempus, Voltus, RedHawk, Calibre).
• Proven experience in sub-system level integration and signoff flows.
• Good understanding of STA, Physical Verification and low-power design methodologies (UPF/CPF).
• Hands on experience with lower process nodes (16nm and below preferred).
• Strong debugging and problem solving skills in timing, congestion and physical verification.
• Hands on experience in handling Analog custom routes, understanding specification to meet R and C.
• Experience in multi-voltage, multi-frequency design.
• Knowledge of EM/IR-drop analysis and mitigation.
• Excellent communication and leadership skills.

Responsibilities

• Lead and own the physical design flow from RTL to GDSII for complex sub-systems.
• Drive floorplanning, power planning, placement, CTS, routing and signoff (timing, IR, EM, DRC/LVS).
• Handle sub-system level PD and provide feedback to full-chip owner.
• Coordinate with block-level PD owners and ensure seamless integration at sub-system level.
• Analyze and optimize PPA to meet design targets.
• Collaborate with RTL, STA, power DFT and verification for design convergence.
• Lead ECO cycles for timing, congestion and physical signoff closure.
• Review and debug physical verification and timing issues.
• Manage schedules, resources and risk tracking for PD deliverables.
• Prepare and present project status, risk and mitigation plans to management and customer.
• Mentor and guide junior engineers in the team.

Skills

ASIC/SoC PD

Lead role

PD tools

Sub-system integration

STA & PV & UPF/CPF

16nm & below

Debugging & timing

Analog routing

Multi-voltage/frequency

EM/IR drop

Communication & leadership

Tools

Innovus

Tempus

Voltus

RedHawk

Calibre

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

Lead Physical Design Engineer

Bayan Lepas, Malaysia | Posted on 10/08/2026

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

Lead and own the physical design flow from RTL - GDSII for complex sub-systems consisting of several blocks.

Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing and signoff (timing, IR, EM, DRC/LVS)

Handle sub-system level PD and provide necessary feedback to full-chip owner.

Coordinate with block-level PD owners and ensure seamless integration at sub-system level.

Analyze and optimize PPA (Power, Performance, Area) to meet design targets.

Collaborate with RTL, STA, power DFT and verification for design convergence.

Lead ECO cycles for timing, congestion and physical signoff closure.

Review and debug physical verification and timing issues.

Manage schedules, resources and risk tracking for PD deliverables.

Prepare and present project status, risk and mitigation plans to management and customer.

Mentor and guide junior engineers in the team.

Requirements

10+ years of experience in ASIC/SOC Physical Design with at least 1+ years in a lead role

Strong expertise in industry standard PD tools (Innovus, Tempus, Voltus, RedHawk, Calibre)

Proven experience in sub-system level integration and signoff flows.

Good understanding of STA, Physical Verification and low-power design methodologies (UPF/CPF)

Hands on experience with lower process nodes (16nm and below preferred)

Strong debugging and problem solving skills in timing, congestion and physical verification

Hands on experience in handling Analog custom routes, understanding specification to meet R and C

Experience in multi-voltage, multi-frequency design

Knowledge of EM/IR-drop analysis and mitigation

Excellent communication and leadership skills