Senior IP Verification Engineer (Vision & SoC)

XPENG; Kuala Lumpur; On-site; MYR 100,000 - 179,000; Full time

Benefits offered by this job

Attractive salary package incl. with a

pension

Bonus potential

Job summary

XPENG in Malaysia is seeking an experienced IP verification engineer to participate in development and verification of core IP modules, plan verification strategies, and drive coverage convergence.

You will build testbenches with SystemVerilog/UVM, develop test cases, and lead a verification team to achieve IP tape-out and delivery, supporting architecture, RTL, and prototype development. The role calls for senior to staff level experience with strong programming and debugging skills.

Qualifications

• Solid academic foundation in digital circuits, integrated circuits, signals and systems, linear algebra, computer architecture, and C programming.
• Familiar with digital IC design and development flows.
• Proficient in Verilog RTL coding and testbench development for simulation.
• Good understanding of AXI, CSI, MIPI, and other related protocols.
• Good understanding of image formats and image processing algorithms.
• Strong programming and debugging capabilities.
• Familiar with mainstream verification methodologies (UVM, SVA, etc.).
• Capable of independently completing full-cycle verification of a brand-new module from scratch.
• 3–10 years of experience in the verification industry (Senior: 3–5 years; Staff: 6–10 years).

Responsibilities

• Participate in the development and verification of core IP modules.
• Plan verification strategies, develop verification plans based on product features, and decompose test points.
• Build testbenches using SystemVerilog/UVM, develop test cases, and drive coverage convergence.
• Complete IP functional, performance, and power verification; support SoC integration verification and gate-level simulation.
• Support verification activities during architecture design, RTL coding, and prototype development.
• Build and manage the verification team, leading the team to achieve successful IP tape-out and delivery (for Staff level).

Skills

Digital IC verification

Verilog RTL

UVM

SystemVerilog

Testbench development

IP verification leadership

Programming debugging

Verification methodologies

Full-cycle verification

Tools

Verilog RTLcoding

UVM

SVA

Job description

XPENG in Malaysia is seeking an experienced IP verification engineer to participate in development and verification of core IP modules, plan verification strategies, and drive coverage convergence.

You will build testbenches with SystemVerilog/UVM, develop test cases, and lead a verification team to achieve IP tape-out and delivery, supporting architecture, RTL, and prototype development. The role calls for senior to staff level experience with strong programming and debugging skills.