Senior ISP ASIC Architect & RTL Lead

XPENG; Kuala Lumpur; On-site; MYR 120,000 - 180,000; Full time

Benefits offered by this job

Pension

Bonus potential

Growth in Europe

Job summary

XPENG in Malaysia is seeking an experienced ISP Architect to own the micro-architecture and RTL of ISP blocks end-to-end, from spec through tape-out. You will lead architecture, PPA trade-offs and collaborate with algorithm, tuning, SW/driver, DV and backend teams.

Responsibilities include silicon bring-up, RTL ECOs, and mentoring engineers while upholding design standards for low power, CDC/RDC and documentation. Prior automotive ISP experience is a plus.

Qualifications

• Bachelor level degree or higher in Microelectronics, Electrical Engineering, Communications, CS or related field.
• 5+ years of digital IC front-end experience with at least one taped-out ISP contribution.
• Strong proficiency in Verilog, SystemVerilog and SVA.
• Proficient with mainstream EDA tools; familiar with JasperGold / VC Formal.
• Solid experience with AMBA protocols and high-bandwidth DMA design.
• Deep understanding of the full camera imaging pipeline and hardware implications.

Responsibilities

• Own the ISP module / sub-system architecture from spec to tape-out and mass production.
• Lead pipeline-level dataflow, buffering strategy and interface design; optimize image quality vs. area, bandwidth and power.
• Collaborate with algorithm, tuning, SW/driver, DV and backend teams on reference models, registers and convergence.
• Lead silicon bring-up, image-quality debugging, root-cause analysis and RTL ECOs for smooth ramp to mass production.
• Mentor mid-level and junior engineers; drive design methodology, code quality, low-power (UPF), CDC/RDC and documentation standards.

Skills

Verilog

SystemVerilog

SVA

EDA tools

AMBA DMA

Camera imaging

CFA patterns

ISP bandwidth

Technical leadership

Education

BS or above in Microelectronics / EE / Communications / CS

Tools

JasperGold

VC Formal

Job description

XPENG in Malaysia is seeking an experienced ISP Architect to own the micro-architecture and RTL of ISP blocks end-to-end, from spec through tape-out. You will lead architecture, PPA trade-offs and collaborate with algorithm, tuning, SW/driver, DV and backend teams.

Responsibilities include silicon bring-up, RTL ECOs, and mentoring engineers while upholding design standards for low power, CDC/RDC and documentation. Prior automotive ISP experience is a plus.