Physical Design Engineer: Low-Node PnR & Tape-out

Russell Tobin; Bayan Lepas; On-site; MYR 180,000 - 240,000; Full time

Job summary

Russell Tobin is seeking an experienced ASIC physical design engineer in Malaysia (Penang/Bayan Lepas) to lead PnR activities from RTL to GDSII. You will develop flows using Perl/TCL, drive floor planning, CTS, routing, and sign-off while solving lower-node challenges to meet performance, area, and power targets.

Ideal candidates have hands-on experience with Synthesis, Floor planning, Clock tree synthesis, Parasitic extraction, STA, and physical verification, plus strong communication skills

Qualifications

• Experience in ASIC PnR (Top/Block level) from RTL to GDSII.
• Hands-on experience with synthesis, floor planning, placement, CTS, routing, STA, parasitic extraction, physical verification and sign-off.
• Excellent communication and presentation skills; ability to collaborate with global teams.
• Ability to drive tasks independently and mentor junior engineers.

Responsibilities

• Develop and implement flow/methodology for PnR using Perl/TCL.
• Work on lower node designs (10nm/7nm/5nm and below) with multiple customers.
• Troubleshoot and optimize physical design for performance, area, and power.

Job description

Russell Tobin is seeking an experienced ASIC physical design engineer in Malaysia (Penang/Bayan Lepas) to lead PnR activities from RTL to GDSII. You will develop flows using Perl/TCL, drive floor planning, CTS, routing, and sign-off while solving lower-node challenges to meet performance, area, and power targets.

Ideal candidates have hands-on experience with Synthesis, Floor planning, Clock tree synthesis, Parasitic extraction, STA, and physical verification, plus strong communication skills