Senior Fusion Compiler Applications Engineer

Synopsys, Inc.; Malaysia; Hybrid; MYR 180,000 - 280,000; Full time

Job summary

Synopsys is seeking an experienced ASIC physical design expert to guide RTL-to-GDS implementation for advanced-node chips. You will work closely with customers and internal teams to ensure tapeout readiness and high-quality results.

You will optimize timing, power, and area using Fusion Compiler, and leverage AI-assisted workflows to accelerate debugging and production efficiency. Strong scripting (Python, Perl, TCL) and experience with Formality/PrimeTime are essential.

Qualifications

• Experience with RTL-to-GDS implementation flows and design optimization.
• Strong scripting skills to automate tasks and improve workflow efficiency.
• Knowledge of advanced-node design challenges and PPA improvements.

Responsibilities

• Support customers through physical design implementation and design closure using Synopsys tools.
• Debug timing, power, and routing challenges at advanced process nodes (7nm and below).
• Provide guidance on best practices for synthesis, place-and-route, and timing closure.
• Develop automation scripts (Python, Perl, TCL) to streamline workflows.
• Collaborate with R&D to reproduce issues and feed use cases back to product teams.
• Present technical solutions to senior customer engineers and design leads.

Skills

RTL-to-GDS flow

ASIC/physical design

Fusion Compiler

Python scripting

Power/timing closure

AI-assisted workflows

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Formality

Formality ECO

PrimeTime

ICC2

Job description

Synopsys is seeking an experienced ASIC physical design expert to guide RTL-to-GDS implementation for advanced-node chips. You will work closely with customers and internal teams to ensure tapeout readiness and high-quality results.

You will optimize timing, power, and area using Fusion Compiler, and leverage AI-assisted workflows to accelerate debugging and production efficiency. Strong scripting (Python, Perl, TCL) and experience with Formality/PrimeTime are essential.