E-core CPU Full Chip Physical Design Engineer

Intel Corporation; Penang; Hybrid; MYR 180,000 - 300,000; Full time

Job summary

Intel Corporation in Penang is seeking a seasoned Full-Chip Physical Design Engineer to drive convergence of FC partitions, floorplanning, pin planning, and power-grid creation. You will coordinate back-end handoffs and drive timing closure with FEV, LVS, DRC, and IR/EM verification.

The role requires leadership and strong collaboration across teams, with a hybrid on-site/off-site work model in Malaysia.

Qualifications

• BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 7 years of experience in CPU physical design and timing verification.
• Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing Tcl scripting Noise, cross-talk, OCV analysis.
• Formal equivalence, DRC/LVS, IR and electro-migration checks.

Responsibilities

• Drive the physical convergence of a Full-Chip (FC) assembly of partitions; perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation.
• Coordinate collateral handoffs between FC Design and back-end disciplines (Clocking, Power Delivery, Partition synthesis/APR).
• Lead physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop/EM analysis).
• Demonstrate leadership, teamwork, and effective communication under aggressive schedules.

Skills

Floorplanning

Timing verification

STA

Leadership

Cross-team collaboration

Education

BS/MS in Electrical/Computer Engineering

Tools

Fusion Compiler

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Tcl scripting

Job description

Job Details: Job Description

Become a key member of a team participating in the physical design construction and integration and verification of a future Intel CPU. This position requires an engineer with broad physical design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team. We are looking for a talented individual to drive the physical convergence of a Full-Chip (FC) assembly of partitions. As a Full Chip design engineer, you will perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation and assembly of partitions.

Given the need for executing multiple projects in parallel, you will be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis). The ideal candidate should have an aptitude to work effectively with EDA tools and exhibit behavioral traits that indicate: Ability to work well in a team and be productive under aggressive schedules Excellent written and verbal communications skills Self-motivation and well organized.

Minimum qualifications

• Must have either BS or MS in Electrical Engineering or Computer Engineering


• Minimum 7 years of experience in CPU physical design and timing verification


• Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing Tcl scripting Noise, cross-talk, OCV analysis. Floorplanning and physical design and timing closure.


• Formal equivalence, DRC/LVS, IR and electro-migration checks

Preferred qualifications

• Has experience with Fusion Compiler, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT

Job Type: Experienced Hire

Shift: Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Job posting details (such as work model, location or time type) are subject to change.

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.