E-core CPU Full Chip Physical Design Engineer

Intel Corporation; George Town; Hybrid; MYR 180.000 - 300.000; Vollzeit

Benefits dieser Stelle

Hybrid work model

Zusammenfassung

Intel Corporation seeks an experienced Full-Chip design engineer to drive floorplanning, pin and feedthrough planning, and multi-project convergence for a high-frequency CPU integration. You will coordinate with back-end groups to ensure robust physical design and timing closure while improving FC methodology.

The role requires leadership to run multiple projects in parallel, strong communication, and hands-on use of EDA tools for optimization, reliability checks, and integration of partitions.

Qualifikationen

• BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 7 years of CPU physical design and timing verification experience.
• Experience with Fusion Compiler, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT is a plus.

Aufgaben

• Perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation, and partition assembly.
• Drive FC methodology efficiency, including floorplan optimization for QoR and timing.
• Coordinate collateral handoffs between FC Design and back-end functions (Clocking, Power Delivery, APR).
• Drive physical design and timing closure (FEV, LVS, DRC, reliability verification such as IR drop/EM).

Kenntnisse

CPU physical design

Timing verification

Tcl scripting

Noise analysis

Cross-talk analysis

Floorplanning

Timing closure

DRC/LVS checks

Electro-migration checks

Ausbildung

BS or MS in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Jobbeschreibung

Job Details:

Job Description:

Become a key member of a team participating in the physical design construction and integration and verification of a future Intel CPU. This position requires an engineer with broad physical design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team. We are looking for a talented individual to drive the physical convergence of a Full-Chip (FC) assembly of partitions.

As a Full Chip design engineer, you will perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation and assembly of partitions. Given the need for executing multiple projects in parallel, you will be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).

The ideal candidate should have an aptitude to work effectively with EDA tools and exhibit behavioral traits that indicate:

• Ability to work well in a team and be productive under aggressive schedules
• Excellent written and verbal communications skills
• Self-motivation and well organized

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:

Must have either BS or MS in Electrical Engineering or Computer Engineering

Minimum 7 years of experience in

• CPU physical design and timing verification
• Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing
• Tcl scripting
• Noise, cross-talk, OCV analysis.
• Floorplanning and physical design and timing closure.
• Formal equivalence, DRC/LVS, IR and electro-migration checks

Preferred qualifications:

• Has experience with Fusion Compiler, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

* Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION:

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.