Senior E-Core CPU Physical Design Engineer (Hybrid)

Intel Corporation; Seberang Perai; Hybrid; MYR 180,000 - 240,000; Full time

Job summary

Intel Corporation in Penang, Malaysia seeks a Senior CPU Physical Design Engineer to drive synthesis, floorplanning, and timing closure for next-gen Atom cores. You will collaborate with RTL, micro-architecture, and circuit teams to optimize performance and power while meeting aggressive schedules in a hybrid work setup.

Requirements include a BS or MS in Electrical or Computer Engineering and 7+ years of CPU physical design experience, with proficiency in Fusion Compiler and PrimeTime.

Qualifications

• Must have BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 7 years of CPU physical design and timing verification experience.
• Experience with Synthesis/APR flows, floorplanning, and timing closure.
• Familiarity with DRC/LVS, IR and electro-migration checks.

Responsibilities

• Perform logic synthesis and place-and-route for CORE IP blocks.
• Conduct floorplanning, routing studies and block-level timing analysis.
• Work on low power techniques and power reduction in sub-systems.
• Physical verification closure of block/sub-system and scripts.
• Collaborate with micro-architecture, RTL and circuit teams to meet targets.

Skills

CPU physical design

Timing verification

Synthesis/APR flows

Tcl scripting

Floorplanning

Physical design

Timing closure

DRC/LVS

Electro-migration checks

IR analysis

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

DCT

DCE

ICC2

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Job description

Intel Corporation in Penang, Malaysia seeks a Senior CPU Physical Design Engineer to drive synthesis, floorplanning, and timing closure for next-gen Atom cores. You will collaborate with RTL, micro-architecture, and circuit teams to optimize performance and power while meeting aggressive schedules in a hybrid work setup.

Requirements include a BS or MS in Electrical or Computer Engineering and 7+ years of CPU physical design experience, with proficiency in Fusion Compiler and PrimeTime.