Senior FPGA Tools & IP Engineer - Lead & Optimize

Altera Corporation; George Town; On-site; MYR 180,000 - 260,000; Full time

Job summary

Altera Corporation in Penang, Malaysia seeks a Senior Technical Lead to drive FPGA IP development, modeling, and verification within the Quartus Prime ecosystem. The role is hands-on with leadership responsibilities, mentoring engineers, and shaping best practices in IP quality, simulation accuracy, and engineering productivity.

The ideal candidate has 8–12+ years in FPGA design/verification, strong RTL skills (Verilog/SystemVerilog/VHDL), and deep familiarity with Quartus Prime.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering or Computer Engineering.
• 8–12+ years of experience in FPGA design, IP development, or verification.
• Hands-on RTL design in Verilog/SystemVerilog/VHDL; strong simulation & verification background.
• Deep experience with Altera Quartus Prime or equivalent FPGA toolchains.
• Ability to debug complex system-level issues and lead technical initiatives.

Responsibilities

• Own technical direction for FPGA IP and simulation models; lead design reviews and validation strategies.
• Develop FPGA IP and high-fidelity simulation models (Behavioral, Cycle-accurate).
• Define and enforce robust verification methodologies (SystemVerilog, assertions).
• Oversee testbench architecture, coverage strategy, and regression systems.
• Drive productivity through automation and regression infrastructure; mentor engineers.

Skills

RTL design

SystemVerilog/VHDL

Simulation & verification

Debugging complex issues

Leadership / mentorship

Automation (Python/Tcl)

Education

Electrical Engineering

Computer Engineering

Tools

Altera Quartus Prime

Job description

Altera Corporation in Penang, Malaysia seeks a Senior Technical Lead to drive FPGA IP development, modeling, and verification within the Quartus Prime ecosystem. The role is hands-on with leadership responsibilities, mentoring engineers, and shaping best practices in IP quality, simulation accuracy, and engineering productivity.

The ideal candidate has 8–12+ years in FPGA design/verification, strong RTL skills (Verilog/SystemVerilog/VHDL), and deep familiarity with Quartus Prime.