Senior NoC IP Architect & RTL Lead

Altera; Bayan Lepas; On-site; MYR 150,000 - 210,000; Full time

Job summary

Altera in Penang, Malaysia seeks a senior FPGA/NOC designer to lead RTL design, simulation, and verification for Network on Chip IPs and related FPGA subsystems integrated into full-chip designs.

The role involves architecture input, prototype creation, and delivering device-level models with timing and power analyses. You will mentor junior engineers, work cross-functionally, and drive excellence in RTL development.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of related working experience.
• Experience in SystemVerilog, VCS/Synopsys simulators, Lint and Synthesis.
• Experience in FPGA design and programming is a plus.

Responsibilities

• Develops logic design, RTL coding, and simulation for Network on Chip IPs and other FPGA IPs for full-chip designs.
• Participates in architecture and microarchitecture feature definition.
• Creates prototypes, simulates models, and specifies system requirements.
• Delivers device-level models and timing/power for bring-up.
• Applies RTL implementation to meet power, performance, and area goals in collaboration with the physical team.
• Reviews verification plans and fixes RTL test failures to ensure feature correctness.
• Grooms next-level technical members and guides the NOC team, anticipating design challenges.

Skills

Leadership

Communication

Problem-solving

RTL validation

NOC IP experience

FPGA design

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

SystemVerilog

VCS/Synopsys simulators

Lint

Synthesis

C/C++/Perl/Python/TCL/Unix Shell

Job description

Altera in Penang, Malaysia seeks a senior FPGA/NOC designer to lead RTL design, simulation, and verification for Network on Chip IPs and related FPGA subsystems integrated into full-chip designs.

The role involves architecture input, prototype creation, and delivering device-level models with timing and power analyses. You will mentor junior engineers, work cross-functionally, and drive excellence in RTL development.