Innovative FPGA IP Design & Verification Engineer

Altera; George Town; Vor Ort; MYR 65.000 - 110.000; Vollzeit

Zusammenfassung

Altera in Penang, Malaysia seeks an FPGA IP Solution Design Engineer to design, develop, and verify high-quality IP for Altera FPGA devices across the full IP lifecycle. You will work on architectural definition, RTL implementation, and customer support, collaborating with cross-functional teams to deliver robust IP solutions.

The role requires strong Verilog/SystemVerilog skills, FPGA architecture knowledge, and hands-on verification experience.

Qualifikationen

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 2+ years of digital IC design with FPGA focus and RTL implementation.
• Proficiency in RTL design using Verilog or SystemVerilog.
• Strong understanding of FPGA architectures and design flows (Quartus Prime, Vivado).
• Experience with verification methodologies (UVM, SystemVerilog Assertions) and simulation tools.
• Familiarity with PCIe, Ethernet, DDR, AXI.
• Experience with Python, Perl, or Tcl scripting.

Aufgaben

• Develop FPGA logic designs, RTL code, and simulations for IP blocks, subsystems, and reusable libraries.
• Define block architecture and microarchitecture translating requirements into FPGA designs.
• Create prototypes, RTL models, and system specs to support feature development and validation.
• Prepare RTL that meets design and test specifications.
• Develop software/hardware models for device bring-up including timing and power behavior.
• Apply RTL techniques to meet power, performance, and area targets with physical-implementation collaboration.
• Design, implement, and maintain FPGA verification environments, testbenches, simulations, and regressions.
• Review verification plans and implementations to ensure features are verified correctly.
• Analyze failing RTL tests to identify root causes and implement corrective actions.
• Integrate and debug Ethernet MAC, PCS/PMA, and protocol-stack functionality on FPGA platforms.
• Bring up and validate FPGA designs on hardware with high-speed interfaces, transceivers, clocks, and board connectivity.
• Use Quartus Prime / Vivado flows for build, timing, programming, and debugging.

Kenntnisse

Verilog

SystemVerilog

FPGA Design

UVM

Python

PCIe

Ethernet

Ausbildung

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Quartus Prime

Vivado

Jobbeschreibung

Altera in Penang, Malaysia seeks an FPGA IP Solution Design Engineer to design, develop, and verify high-quality IP for Altera FPGA devices across the full IP lifecycle. You will work on architectural definition, RTL implementation, and customer support, collaborating with cross-functional teams to deliver robust IP solutions.

The role requires strong Verilog/SystemVerilog skills, FPGA architecture knowledge, and hands-on verification experience.