Senior FPGA Soft IP Architect – High-Speed Interfaces

Altera Corporation; Kuala Lumpur; On-site; MYR 180,000 - 240,000; Full time

Job summary

Altera Corporation in Malaysia seeks a Senior FPGA Soft IP Design Engineer to architect, develop, and productize FPGA Soft IP cores for Quartus and Platform Designer. You will own parameterizable RTL from specification to catalog release, balancing PPA and interfaces, and guiding junior engineers.

Experience with JESD204B/C or Ethernet is a strong plus. This is an experienced individual contributor role requiring hands-on design, verification, and collaboration with cross-functional teams to

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or related field.
• Bachelor’s + 6 years, or Master’s + 4 years, of FPGA/ASIC RTL or Soft IP design.
• Strong proficiency in parameterizable RTL using Verilog, SystemVerilog, and/or VHDL.
• Proven experience taking IP through synthesis, simulation, timing constraints (SDC), CDC, and STA.
• Experience packaging or integrating IP in Platform Designer / Qsys, Vivado IP Integrator, or similar IP catalog flow.
• Familiarity with AXI4 / AXI-Stream, Avalon-MM / Avalon-ST, CSR/register interfaces.
• Experience with scripting for IP generation, regression, and design automation (Python, Tcl, and/or Perl).
• Proficiency with version control (Git) and structured code review.
• Strong debug, problem-solving, and written/verbal communication skills; able to work independently and lead technical discussions across sites.

Responsibilities

• Architect, design, and implement FPGA Soft IP cores in VHDL, Verilog, or System Verilog, targeting high performance, low resource usage, and timing closure across Altera device families.
• Develop parameterizable, reusable IP with clean configuration spaces, documented interfaces, and stable upgrade behavior across Quartus releases.
• Own the Soft IP lifecycle: RTL design, synthesis, functional simulation, lint, CDC analysis, STA, and example-design bring-up.
• Package IP for Quartus / Platform Designer (Qsys), including metadata, HDL generation, parameter validation, and integration with Native PHY, transceiver, and interconnect IP.
• Define and implement register maps, CSR/AXI-Lite or Avalon-MM control interfaces, reset and clocking schemes, and user-facing data interfaces (AXI-Stream, Avalon-ST, or equivalent).
• Design and maintain simulation testbenches, directed and constrained-random tests, assertions, and regression suites that prove protocol compliance and configuration coverage.
• Collaborate with verification, firmware, software, and hardware teams on memory maps, configuration sequences, example designs, and hardware validation on FPGA development kits.
• Debug IP issues across simulation, synthesis, place-and-route, and hardware; drive root-cause analysis and timely customer or release fixes.
• Author and review design specifications, user guides, release notes, and API/register documentation for internal teams and external customers.
• Lead technical reviews, enforce coding and quality standards, and mentor junior Soft IP designers.
• Support customer inquiries, FAEs, and design-in issues related to Soft IP behavior, integration, and performance.
• Contribute to development-flow and quality improvements (lint/CDC/STA methodology, automation, IP upgrade robustness).

Skills

Verilog

SystemVerilog

VHDL

RTL design

CDC/STA

Python

Tcl

Perl

Git

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Quartus

Platform Designer / Qsys

Vivado IP Integrator

Synthesis tools

Job description

Altera Corporation in Malaysia seeks a Senior FPGA Soft IP Design Engineer to architect, develop, and productize FPGA Soft IP cores for Quartus and Platform Designer. You will own parameterizable RTL from specification to catalog release, balancing PPA and interfaces, and guiding junior engineers.

Experience with JESD204B/C or Ethernet is a strong plus. This is an experienced individual contributor role requiring hands-on design, verification, and collaboration with cross-functional teams to