Senior FPGA Dev Tools Engineer | Validation & Automation

Altera; George Town; On-site; MYR 150,000 - 250,000; Full time

Job summary

Altera in Penang, Malaysia is seeking a senior engineer for the Device Modeling & Enablement team to develop and automate tests validating FPGA device and simulation models used by Quartus Prime. You will drive end-to-end validation flows, build regression infrastructure, analyze results, and collaborate with design teams to ensure high-quality releases.

The ideal candidate has a strong foundation in digital design and hands-on experience with FPGA/ASIC flows, plus automation and debugging

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4-5 year of relevant experience.
• Strong foundation in digital design principles: combinational/sequential logic, clocking, resets, pipelining.
• Experience with FPGA or ASIC flows: RTL (Verilog/SystemVerilog or VHDL), synthesis, static timing analysis, and constraints (SDC).
• Proficiency in at least one scripting language (Tcl or Python) and a working foundation in C++ for developing or debugging hardware or device models.
• Familiarity with Linux development environments and build workflows.
• Strong problem-solving skills with the ability to interpret tool logs and timing reports.
• Effective written communication for documentation and clear defect reporting.

Responsibilities

• Develop comprehensive test plans for device and simulation model validation across Quartus Prime components.
• Execute targeted and regression tests across multiple FPGA device families, configurations, and corner cases.
• Ensure verification coverage aligns with design intent and release quality goals.
• Build and run end-to-end Quartus projects to exercise synthesis, fitting, and simulation signoff on representative designs.
• Maintain golden reference results; compare and triage deltas in QoR, performance, resource utilization, and warnings/errors.
• Package and maintain reproducible test kits and reference designs.
• Create and maintain automation and modeling tools using C++, Tcl, Python, and bash for test generation, execution, log mining, and results reporting.
• Develop and maintain C++ device model libraries representing FPGA architecture blocks such as DSP and memory used by synthesis and simulation flows.
• Integrate tests and model validation into CI pipelines, including pass/fail gates and artifact tracking.
• Develop utilities to parameterize devices, architectural variants, corners, and random seeds for coverage expansion.
• Analyze failures across synthesis, fitter, and device models; isolate root causes and validate fixes with teams.

Skills

Digital design

FPGA flows

Automation

C++

Python

Tcl

Linux

Debugging

CI pipelines

Education

BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Git

Quartus Prime

TimeQuest

Job description

Altera in Penang, Malaysia is seeking a senior engineer for the Device Modeling & Enablement team to develop and automate tests validating FPGA device and simulation models used by Quartus Prime. You will drive end-to-end validation flows, build regression infrastructure, analyze results, and collaborate with design teams to ensure high-quality releases.

The ideal candidate has a strong foundation in digital design and hands-on experience with FPGA/ASIC flows, plus automation and debugging