Senior FPGA Verification Lead

Altera Corporation

George Town

Vor Ort

MYR 180.000 - 300.000

Vollzeit

Vor 3 Tagen
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Zusammenfassung

Altera is seeking a Lead Design Verification Engineer in Penang to drive functional verification of FPGA designs, develop verification plans and test benches, and ensure coverage meets microarchitecture specifications.

You will execute verification plans, run system simulations, debug issues, and collaborate with FPGA architects, RTL developers and physical design teams to improve verification of complex features.

Qualifikationen

  • Bachelor's/Master's/PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience.
  • Experience in Pre Silicon Validation/Verification.
  • Proficient with OVM/UVM, SystemVerilog, constrained random verification methodologies.

Aufgaben

  • Perform functional logic verification of an FPGA to ensure design meets specifications.
  • Develop verification plans, test benches, and verification environments to ensure coverage.
  • Execute verification plans, run system simulations, analyze power and timing, and debug issues in pre-silicon environment.
  • Collaborate with FPGA architects, RTL developers, and physical design teams to improve verification of complex features.
  • Document test plans, reviews, and verification strategy plans across methodologies.
  • Maintain and improve verification infrastructure and methodology.

Kenntnisse

OVM/UVM
SystemVerilog
Constrained random verification
Pre-silicon validation/verification
Debugging and diagnostics

Ausbildung

BS/MS/PhD in Electrical or Computer Science Engineering or related field

Tools

PCIe/UCIe PHY Verification

Jobbeschreibung

Altera is seeking a Lead Design Verification Engineer in Penang to drive functional verification of FPGA designs, develop verification plans and test benches, and ensure coverage meets microarchitecture specifications.

You will execute verification plans, run system simulations, debug issues, and collaborate with FPGA architects, RTL developers and physical design teams to improve verification of complex features.

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