Senior Design Verification Engineer

Oppstar Berhad; Penang; On-site; MYR 60,000 - 90,000; Full time

Job summary

Oppstar Berhad in Penang, Malaysia is seeking a verification engineer to perform pre-Si verification on IP blocks and full-chip FPGA/ASIC designs.

You will define test plans, develop SystemVerilog/UVM testbenches and content, and debug and run regressions to deliver high-quality design validation. You will work closely with IP architects, logic design engineers, and design automation specialists to ensure robust verification flows.

Qualifications

• Experience in functional verification including test planning and bench development.
• 2

Responsibilities

• Define test plans and develop SystemVerilog/UVM testbenches.
• Debug and run regression to ensure high-quality validation.

Skills

Functional verification

SystemVerilog UVM

Constrained random verification

Assertion-based verification

Education

BSEE

MSEE

PhD

Tools

Cadence

Mentor Graphics

Synopsys

Job description

• Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
• The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
• Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.

Qualifications:

• BSEE/MSEE/PhD with at least 4 years' relevant experience
• Experience in functional verification that may includes test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.
• Experience with modern verification techniques e.g. SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies.
• Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.
• Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.