Senior Analog & Mixed-Signal Layout Engineer

Altera; Penang; On-site; MYR 120,000 - 210,000; Full time

Job summary

Altera is seeking an experienced Analog Layout Design Engineer in Penang to lead the physical design and layout of complex analog and mixed-signal ICs. You will collaborate with circuit designers to meet performance targets and oversee layout schedules, ensuring manufacturability and reliability.

The role requires a strong background in transistor-level layout, proficiency with Cadence Virtuoso and Mentor Graphics, and a track record mentoring junior engineers.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 8+ years of experience in analog/mixed-signal IC layout design.
• Expert proficiency with Cadence Virtuoso and Mentor Graphics.
• Deep understanding of transistor-level and analog circuit topologies and their layout sensitivities.
• Excellent communication and collaboration in cross-functional teams.

Responsibilities

• Lead and execute layout design of analog and mixed-signal circuits.
• Collaborate with circuit designers to understand requirements and targets.
• Plan schedules and deliverables; manage layout resources.
• Perform floorplanning, placement, and routing; optimize for area and performance.
• Conduct DRC, LVS, ERC including RV.
• Mentor junior layout engineers and drive design reviews.
• Interface with foundry to ensure DRC compliance and best practices.
• Document layout methodology and guidelines for future projects.

Skills

Analog layout design

Team leadership

Problem-solving

Education

Bachelor's or Master's degree in Electrical Engineering or Microelectronics

Tools

Cadence Virtuoso

Mentor Graphics

Job description

Altera is seeking an experienced Analog Layout Design Engineer in Penang to lead the physical design and layout of complex analog and mixed-signal ICs. You will collaborate with circuit designers to meet performance targets and oversee layout schedules, ensuring manufacturability and reliability.

The role requires a strong background in transistor-level layout, proficiency with Cadence Virtuoso and Mentor Graphics, and a track record mentoring junior engineers.