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Altera is seeking an experienced Analog Layout Design Engineer to lead the FPGA physical design and layout of complex digital, analog and mixed-signal ICs in Penang, Malaysia.
You will collaborate with circuit designers, plan layout schedules, perform floorplanning, routing, and physical verification (DRC, LVS, ERC). Mentoring junior engineers and coordinating with foundries are key aspects of the role.
We are seeking a highly skilled Analog Layout Design Engineer to join our dynamic team. The successful candidate will be responsible for leading the FPGA physical design and layout of complex digital, analog and mixed-signal integrated circuits (ICs), ensuring optimal performance, reliability, and manufacturability.
Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.
About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.