Senior Custom Layout Engineer – Analog/Mixed-Signal

Infinecs Systems Pvt. Ltd.; Bayan Lepas; On-site; MYR 67,000 - 134,000; Full time

Job summary

Infinecs Systems Pvt. Ltd. in Bayan Lepas, Penang is seeking a Layout Engineer to design analog mixed-signal circuits per project requirements.

You will perform block-level physical implementation including floor-planning, power distribution, clock and signal routing, and analog/mixed-signal transistor-level layout. You will also participate in post-layout analysis and potential block/IP/chip integration activities.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or related field.
• Minimum 3+ years of experience in custom layout design including mixed-signal design.
• Experience with Cadence Virtuoso Layout Suite or similar EDA tools is a must.
• Proven expertise in physical verification using LVS and DRC tools.
• In-depth knowledge of CMOS process technologies.
• Good understanding of analog and mixed signal layout fundamentals.
• Excellent problem-solving and analytical skills.
• Meticulous attention to detail and a commitment to quality.
• Effective communication and collaboration skills.

Responsibilities

• Layout design of analog mixed signal circuit per project requirements.
• Block level physical implementation including floor-planning and routing.
• Post-layout circuit performance analysis.
• Participation in block/IP/chip level integration activities.
• Define layout methodology and flow.

Skills

Analog layout

Analytical skills

Problem-solving

Communication

Education

Bachelor's in Electrical/Computer Engineering

Tools

Cadence Virtuoso Layout Suite

LVS

DRC

Job description

Infinecs Systems Pvt. Ltd. in Bayan Lepas, Penang is seeking a Layout Engineer to design analog mixed-signal circuits per project requirements.

You will perform block-level physical implementation including floor-planning, power distribution, clock and signal routing, and analog/mixed-signal transistor-level layout. You will also participate in post-layout analysis and potential block/IP/chip integration activities.