Senior Analog Layout Architect - Full-Chip Lead

SkyeChip Berhad

Penang

On-site

MYR 180,000 - 300,000

Full time

6 days ago
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Benefits offered by this job

Stock options
Career advancement opportunities
Competitive pay and benefits

Job summary

SkyeChip Berhad seeks an experienced Custom Analog Layout Engineer in Malaysia to lead AMS layout efforts across on-site Penang, Selangor and Vietnam sites. You will mentor, coordinate with circuit/physical teams, and drive layout quality for complex analog/mixed-signal ICs.

8–10+ years of hands-on layout, deep-submicron experience, and proficiency in Cadence Virtuoso and Calibre are expected. Opportunity for growth in a dynamic startup environment with competitive pay.

Qualifications

  • 8–10+ years in custom microelectronics layout design.
  • Proven floor planning and full-chip integration for analog/mixed-signal ICs.
  • Hands-on in sub-5nm processes and CMOS tape-outs.
  • Strong understanding of layout effects on performance.
  • Experience with DRC, LVS, and parasitic optimization.
  • Proficient with Cadence Virtuoso and Synopsys Custom Compiler.

Responsibilities

  • Lead layout teams through all project phases from planning to tape out.
  • Perform floor planning and full-chip layout for AMS ICs.
  • Collaborate with circuit and physical design to ensure quality.
  • Mentor mid and junior layout engineers.
  • Address layout challenges including DRC, LVS, and electromigration.
  • Track schedules and coordinate cross-functional activities.
  • Participate in reviews to ensure manufacturability.
  • Drive automation improvements in layout methodology.

Skills

AMS layout
Deep sub-micron
Scripting: Python
Scripting: Tcl
Mentorship
Layout leadership

Tools

Cadence Virtuoso
Synopsys Custom Compiler
ICV/Calibre

Job description

SkyeChip Berhad seeks an experienced Custom Analog Layout Engineer in Malaysia to lead AMS layout efforts across on-site Penang, Selangor and Vietnam sites. You will mentor, coordinate with circuit/physical teams, and drive layout quality for complex analog/mixed-signal ICs.

8–10+ years of hands-on layout, deep-submicron experience, and proficiency in Cadence Virtuoso and Calibre are expected. Opportunity for growth in a dynamic startup environment with competitive pay.

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