Power Integrity Engineer

UST Global (M) Sdn Bhd; Bayan Lepas; On-site; MYR 67,000 - 100,000; Full time

Job summary

UST Global (M) Sdn Bhd is seeking a Power Integrity Engineer to perform end-to-end simulations for high-speed platforms, boards, and silicon. You will analyze PDNs with 2D/3D model extraction and noise considerations across die, package, sockets, and boards.

The role requires a degree in Electronics, 1-2 years of experience (fresh grads welcome), and strong analytical and communication skills. Proficiency with Cadence Sigrity, Hspice, ADS, JMP, MATLAB, and Ansys SI Wave is preferred.

Qualifications

• Bachelor’s Degree in Electronic Engineering or closely related discipline.
• CGPA minimum 3.30/4.00.
• 1-2 years of relevant experience; fresh graduates encouraged.
• Strong interest in electronics, circuit design, and power delivery networks.
• Good analytical, problem-solving and communication skills.
• Willingness to learn new simulation tools and engineering methodologies.

Responsibilities

• Conduct power integrity simulations end to end for high-speed platforms, boards, packages, and silicon.
• Analyze power delivery networks using 2D/3D model extraction and noise analysis.
• Apply PI design knowledge to simulate routing, package, and platform implementations.
• Deliver platform-level power shapes and decoupling solutions as part of the design guide.

Skills

1-2 years experience

Fresh graduates welcome

Strong interest in electronics

Analytical and problem-solving

Good communication

Willingness to learn

Education

Bachelor’s Degree in Electronic Engineering

Tools

Cadence Sigrity

ADS

Hspice

JMP

SIGMA MATLAB

Layout Viewer

Ansys SI Wave

Job description

Conduct power integrity (PI) simulations from end to end (highspeed platforms, boards, packages, and silicon).

Analyzes power delivery networks including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards.

Applies knowledge of power integrity design and tradeoffs to perform simulations of power network routing, guide package, and platform physical implementation.

Delivers platform level power shapes and decoupling solutions as part of the platform design guide.

Requirements:

• At least have a minimum of 1-2 years of relevant experience
• Fresh graduates are encouraged to apply.
• Bachelor’s Degree in Electronic Engineering or a closely related discipline.
• Minimum CGPA of 3.30/4.00.
• Strong interest in electronics, circuit design, power delivery networks, and signal/power integrity.
• Good analytical, problem-solving, and communication skills.
• Willingness to learn new simulation tools and engineering methodologies.
• Experience with Cadence Sigrity , ADS, Hspice, JMP, SIGMA(Matlab), Layout Viewer, Hspice, JMP, Cadence Sigrity, Ansys SI wave are good to have.