Signal Integrity Engineer

UST Malaysia; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Malaysia in Penang is seeking a senior SI/PI engineer to perform system-level power integrity analysis, PDN model extraction, and development of board-level power delivery networks. You will conduct DC, AC, and transient simulations and review layouts in Cadence Allegro, ensuring signal integrity across high-speed interfaces.

5–10 years of SI/PI experience required. Proficiency with PowerSI, PowerDC, ADS, HSPICE, HFSS, and familiarity with IBIS-AMI modeling and jitter/equalization techniques

Qualifications

• 5–10 years of experience in SI/PI field.
• Experience with system-level PI/PDN analysis and board-level PDN modeling.
• Experience reviewing layouts in Cadence Allegro and performing high-speed SI/PI analysis.

Responsibilities

• Perform system-level PI analysis including extraction and development of PDN models.
• Conduct DC, AC, and transient simulations using PowerSI, PowerDC, ADS, and HSPICE.
• Perform SI analysis for high-speed interfaces across package, PCB, and connectors.
• Review package and PCB layouts in Cadence Allegro.

Skills

Power integrity

Signal integrity

DC/AC/transient simulation

PDN modeling

End-to-end channel analysis

IBIS-AMI modeling

Jitter analysis

CTLE/DFE/FFE equalization

Tools

PowerSI

PowerDC

ADS

HSPICE

HFSS

Cadence Allegro

Job description

Perform system-level power integrity (PI) analysis, including extraction and development of package- and board-level PDN models and construction of system-level power delivery networks; conduct DC, AC, and transient simulations using PowerSI, PowerDC, ADS, and HSPICE.

Perform signal integrity (SI) analysis for high-speed interfaces (e.g., DDR/LPDDR, PCIe, USB, SerDes, Ethernet) across package, PCB, and connector interconnects, using HFSS for model extraction and ADS for end-to-end channel analysis; working knowledge of IBIS-AMI modeling, jitter analysis, and equalization techniques (e.g., CTLE, DFE, FFE) preferred.

Review package and PCB layouts in Cadence Allegro.

Working experience : 5- 10 years in SI/PI field