SI/PI Engineer (Signal Integrity / Power Integrity)

Infinecs Systems Pvt. Ltd.; Bayan Lepas; Sur place; MYR 120 000 - 180 000; Plein temps

Résumé du poste

Infinecs Systems Pvt. Ltd. in Bayan Lepas, Penang, Malaysia, seeks a senior engineer to perform system-level Power Integrity and Signal Integrity analyses for high-speed interfaces such as DDR/LPDDR, PCIe, USB, SerDes, and Ethernet.

You will extract interconnect models with HFSS, review package/PCB layouts, and apply jitter analysis and equalization techniques (CTLE, DFE, FFE) to optimize designs.

Qualifications

• Bachelor's degree or higher in Electrical/ Electronics Engineering or a related field.
• 5+ years of experience in Signal Integrity and Power Integrity engineering.
• Hands-on experience in SI/PI analysis, simulation, and package- and board-level modeling.
• Experience with high-speed interface analysis and package/PCB layout review.
• Proficiency in SI/PI simulation tools: PowerSI, PowerDC, ADS, HFSS, and HSPICE.
• Working knowledge of IBIS-AMI modeling.
• Experience in jitter analysis and signal equalization techniques (CTLE, DFE, FFE).

Responsabilités

• Perform system-level PI analysis including PDN modeling at package- and board-level.
• Conduct DC, AC, and transient simulations using PowerSI, PowerDC, ADS, and HSPICE.
• Perform SI analysis for DDR/LPDDR, PCIe, USB, SerDes, and Ethernet.
• Extract interconnect models using HFSS and conduct end-to-end channel analysis using ADS.
• Review package and PCB layouts using Cadence Allegro.
• Apply IBIS-AMI modeling, jitter analysis, and equalization techniques (CTLE, DFE, FFE).

Connaissances

Power Integrity

Signal Integrity

PI/SI analysis

Package/board modeling

High-speed interfaces

Interconnect modeling

Formation

Bachelor's degree in Electrical/ Electronics Engineering

Outils

PowerSI

PowerDC

ADS

HFSS

HSPICE

IBIS-AMI modeling

Description du poste

• Perform system-level Power Integrity (PI) analysis, including package- and board-level Power Delivery Network (PDN) modeling.
• Conduct DC, AC, and transient simulations using PowerSI, PowerDC, ADS, and HSPICE.
• Perform Signal Integrity (SI) analysis for high-speed interfaces such as DDR/LPDDR, PCIe, USB, SerDes, and Ethernet.
• Extract interconnect models using HFSS and conduct end-to-end channel analysis using ADS.
• Review package and PCB layouts using Cadence Allegro.
• Apply knowledge of IBIS-AMI modeling, jitter analysis, and equalization techniques such as CTLE, DFE, and FFE.

Requirements

• Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a related field.
• Minimum 5 years of relevant experience in Signal Integrity (SI) and Power Integrity (PI) engineering.
• Hands-on experience in SI/PI analysis, simulation, and package- and board-level modeling.
• Experience with high-speed interface analysis and package/PCB layout review.
• Proficiency in relevant SI/PI simulation tools, including PowerSI, PowerDC, ADS, HFSS, and HSPICE.
• Working knowledge of IBIS-AMI modeling.
• Experience in jitter analysis and signal equalization techniques, including CTLE, DFE, and FFE.