Power Integrity (PI) Engineer (Mid-Level / Senior)

Oppstar Technology; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Oppstar Technology in Penang seeks a Power Integrity (PI) Engineer at mid-level or senior level to support end-to-end PDN analysis across complex boards and platforms. The role emphasizes optimizing power delivery, rail stability, and sign-off readiness for next-gen hardware.

You will conduct PDN impedance and 2D/3D model extractions, run DC/IR drop simulations, and drive decoupling optimization with actionable mitigation recommendations. On-site work is required in Penang.

Qualifications

• Education in Electrical & Electronics Engineering, Microelectronics, Physics or related field.
• Senior: 5+ years in PI simulation and PDN design; Mid: 2–4 years in PI/SI.
• Proficiency with PI tools such as Cadence Sigrity, Ansys SIwave/HFSS.
• Strong foundation in VRM stability, impedance methodology, decoupling and resonance mitigation.

Responsibilities

• PDN impedance analysis and 2D/3D model extraction across boards and packages.
• DC/IR drop simulations to ensure rail voltage stays within specs.
• Drive decoupling capacitor optimization and resonance mitigation.
• Provide guidance on physical routing and power shape decisions.
• Produce PI analysis reports and support cross-functional sign-off before tape-out.

Skills

PDN analysis

IR drop

Decoupling optimization

Power integrity

Education

Bachelor's or Master's in Electrical & Electronics Engineering / Microelectronics / Physics

Tools

Cadence Sigrity (PowerDC / OptimizePI)

Ansys SIwave

Ansys HFSS

Job description

Power Integrity (PI) Engineer (Mid-Level / Senior)

About the Role

We are seeking Senior and Mid-Level Power Integrity (PI) Engineers in Penang to support end-to-end Power Delivery Network (PDN) analysis and simulation across complex custom boards, packages, and high-speed computing platforms. You will play a critical role in optimizing power delivery architectures, ensuring rail stability, and achieving sign-off readiness for next-generation hardware platforms.

Key Responsibilities

PDN & Impedance Analysis: Conduct 2D and 3D model extraction, PDN impedance analysis, and noise analysis across die/C4 bumps, silicon, packages, sockets, and multi-layer PCBs (up to 16 layers).

DC / IR Drop Simulation: Perform DC/IR drop simulations across critical power rails to ensure voltage tolerances remain strictly within target specifications.

Decoupling & Resonance Optimization: Drive AC decoupling capacitor optimization to meet target impedance profiles across frequency ranges, deliver optimized capacitor BOMs, and perform power plane resonance analysis with actionable mitigation recommendations.

Physical Implementation Guidance: Apply power integrity design tradeoffs to guide package and platform physical routing, delivering platform-level power shapes and decoupling solutions.

Reporting & Sign-Off: Generate comprehensive PI analysis reports, support data correlation, and collaborate with cross-functional design teams to close out critical issues prior to board tape-out.

Requirements & Qualifications

Education: Bachelor's or Master's Degree in Electrical & Electronics Engineering, Microelectronics, Physics, or a related discipline.

Experience Level:

Senior Level: 5+ years of dedicated experience in Power Integrity simulation and PDN design.

Mid-Level: 2–4 years of hands-on experience in PI/SI simulations (candidates who can work with initial guidance and transition into independent execution are strongly encouraged to apply).

EDA Tool Proficiency: Proficiency with PI and electromagnetic simulation tools including Cadence Sigrity (PowerDC / OptimizePI), Ansys SIwave, or Ansys HFSS.

Technical Expertise: Strong foundation in VRM stability, PDN target impedance methodology, decoupling capacitor selection, and power plane resonance mitigation.

Work Arrangement: Ability to work full-time on-site in Penang and deliver high-quality simulation reports within scheduled project milestones.