Senior Physical Design Engineer – PCIe & AI Chip

Bitdeer (NASDAQ: BTDR); Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Bitdeer is seeking a Senior Physical Design Engineer in Penang to drive the full physical implementation of high-speed PCIe IP and sub-systems for AI chips. You’ll collaborate across RTL, DFT and verification teams to deliver silicon-proven designs on advanced nodes.

Ideal candidates bring 5+ years in physical design, strong CTS/PD experience, and hands-on P&R/timing skills with Cadence Innovus, Synopsys Primetime, and related tools.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands-on physical design experience in advanced TSMC process nodes (N6 and below preferred).
• Strong knowledge of PCIe protocol and high-speed interface physical design constraints.
• CTS strategies, skew balancing, useful skew and multi-corner CTS closure.
• CTS for high-speed designs: CTS strategies, skew balancing, useful skew and multi-corner CTS closure.
• Hands-on proficiency with PnR and timing signoff tools (Cadence Innovus / Synopsys Primetime / Tweaker).
• Experience in resolving chip level DRC / LVS / EMIR issues for advance nodes.
• Experience in multi-die packaging (WoW, 2.5D / 3D), Thermal / IR / EM signoff, signal integrity, or DFT-aware physical design is plus.
• Proficiency using Python, Perl, Tcl, Make scripting is plus.
• Tape out experience required.

Responsibilities

• Own end-to-end physical design flow: floorplanning, placement, CTS, routing, STA, physical verification and signoff for PCIe controller and PHY blocks.
• Perform timing closure for high-speed PCIe Gen 4/5/6 interfaces across PVT corners.
• Drive power integrity analysis including IR drop and electromigration (EM) across the power delivery network.
• Achieve physical verification closure including DRC, LVS, and ERC signoff using Calibre tool.
• Work with RTL and synthesis teams to provide feedback on logic restructuring for timing and area improvement.
• Contribute to internal PD methodology, scripts, and flow automation using Perl and Tcl.
• Support tapeout activities including final GDS merge, fill insertion, and signoff checks.

Skills

Physical design experience

PCIe high-speed

CTS strategies

P&R timing

DRC/LVS/EMIR

Multi-die packaging

Thermal/EM signoff

Python/Perl/Tcl

Tape-out experience

Education

Electrical/Computer Engineering degree

Tools

Cadence Innovus

Synopsys Primetime

Tweaker

Job description

Bitdeer is seeking a Senior Physical Design Engineer in Penang to drive the full physical implementation of high-speed PCIe IP and sub-systems for AI chips. You’ll collaborate across RTL, DFT and verification teams to deliver silicon-proven designs on advanced nodes.

Ideal candidates bring 5+ years in physical design, strong CTS/PD experience, and hands-on P&R/timing skills with Cadence Innovus, Synopsys Primetime, and related tools.