Staff SoC RTL/Logic Engineer - Drive IP Integration

Intel Corporation; Penang; On-site; MYR 150,000 - 220,000; Full time

Job summary

Intel Corporation's Devices Development Group Malaysia (DDG-MYS) is seeking a SoC RTL/Logic Staff Design Engineer to contribute to next-generation Client SoC development. You will own internal IP RTL design, integrate high-performance IP, and collaborate with verification teams to ensure pre-silicon readiness and seamless SoC integration in Malaysia, Penang.

This role requires on-site work and strong RTL/Verilog/SystemVerilog expertise.

Qualifications

• Bachelor or Master degree in Electrical and Electronic Engineering, Computer Engineering, or Computer Science.
• At least 3 years of experience in IP or SoC RTL/Logic Design.
• Strong knowledge of IP/subsystem architecture and high-speed bus protocols.
• Experience with Verilog/SystemVerilog and RTL verification workflows.

Responsibilities

• Own DDG internal IP RTL design and development or integrate high-performance IP into Client SoC platforms.
• Define, implement, and deliver new IP features, change requests, and feature enhancements.
• Drive IP-to-SoC handoff quality, ensuring design completeness, compliance, and readiness for downstream integration.
• Perform logic and RTL integration into SoC, including power intent definition, signal handling across power planes and clock domains, and delivery of front-end collateral for system and software integration.
• Develop design solutions and collaborate closely with verification teams to validate functionality, features, and integration readiness.
• Execute front-end quality checks across RTL static analysis, synthesizability, timing and power convergence, netlist quality, formal equivalence verification, and related design quality milestones.

Skills

Verilog

SystemVerilog

IP/SoC integration

RTL/Logic design

Education

Bachelor or Master Degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science

Job description

Intel Corporation's Devices Development Group Malaysia (DDG-MYS) is seeking a SoC RTL/Logic Staff Design Engineer to contribute to next-generation Client SoC development. You will own internal IP RTL design, integrate high-performance IP, and collaborate with verification teams to ensure pre-silicon readiness and seamless SoC integration in Malaysia, Penang.

This role requires on-site work and strong RTL/Verilog/SystemVerilog expertise.