Lead Engineer - PD

Quest Global; Bayan Lepas; On-site; MYR 180,000 - 240,000; Full time

Benefits offered by this job

Competitive Benefit

Job summary

Quest Global in Malaysia is seeking an experienced Physical Design leader with 10+ years in PD and a bachelor’s degree in Electronics Engineering. You will guide a team of engineers through PD flows from RTL to GDS, optimize timing using Innovus, and develop PD scripts to improve efficiency.

The role involves leading multiple engineers, working with FinFET/dual-patterning nodes, and developing dashboards for QOR metrics to ensure timely delivery and quality.

Qualifications

• 10+ years of experience in Physical Design (PD) from RTL to GDS flow.
• Ability to lead a team of 5+ engineers.
• Experience in PD metrics dashboards for QOR tracking.
• Experience in modifying STA constraints to check timing closure.

Responsibilities

• Lead a team of at least 5 engineers to execute PD flows.
• Manage physical design from RTL to GDS flow and optimize timing and power.
• Develop and modify PD-EDA tool scripts using TCL/SHELL/PYTHON.
• Develop PD metrics dashboards for QOR tracking.
• Modify STA constraints to ensure timing closure feasibility.
• Implement clocking strategies (CTS, Flex-H, Custom-CTS) for latency and skew targets.
• Work with FinFET & Dual Patterning nodes (16/14/10/7/5/3nm).

Skills

Team leadership

Timing optimization

Scripting (TCL/SHELL/PYTHON)

Education

Bachelor’s degree in Electronics Engineering or equivalent

Tools

Innovus

PD-EDA tools scripts

Job description

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

10+ years’ experience with bachelor’s degree in Electronics Engineering or equivalent

• Experience in Physical Design with PNR flow from RTL to GDS flow,
• Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.
• Hands‑on experience in developing and modifying PD‑flow/EDA‑tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
• Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
• Experience in modifying STA constraints to check timing closure feasibility
• Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Work Experience

• 10+ years’ experience with bachelor’s degree in Electronics Engineering or equivalent
• Ability to lead a team of min 5 engineers to execute.
• Experience in Physical Design with PNR flow from RTL to GDS flow,
• Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.
• Hands‑on experience in developing and modifying PD‑flow/EDA‑tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
• Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
• Experience in modifying STA constraints to check timing closure feasibility
• Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm

Benefits

• Competitive Benefit