Staff DFT Design Engineer

Altera; George Town; On-site; MYR 180,000 - 360,000; Full time

Job summary

Altera in Malaysia is seeking a senior DFT Architect to lead end-to-end DFT strategy for complex FPGA designs. You will drive architecture, RTL, and testability decisions, mentor engineers, and align DFT with safety and manufacturing goals.

The role requires 10+ years in DFT, strong Verilog/SystemVerilog skills, and experience with AI/LLM-assisted DFT improvements. Join a global team delivering scalable, high-quality test solutions.

Qualifications

• Bachelor’s or Master’s degree in Electrical / Electronic Engineering or related field.
• 10+ years of industry experience in DFT design with hands-on ownership.
• Strong experience in DFT methodology, architecture & design in custom design blocks & PNR flows.
• Proven ability to drive collaboration across architecture, RTL, PD, test, and manufacturing teams.
• Strong Verilog and/or SystemVerilog proficiency.
• Excellent technical communication and decision-making skills.
• Good debugging, problem-solving, and communication skills.
• Proven track record in driving AI or LLM to simplify or enhance DFT implementations in FPGA or SOC design.

Responsibilities

• Define end-to-end DFT architecture and strategy for FPGA designs and platforms.
• Drive DFT requirements at architecture and RTL definition stages, influencing design trade-offs early.
• Own DFT methodology evolution, including scalability, reuse, and long-term roadmap alignment.
• Lead design reviews and collaborate with stakeholders to drive closure.
• Provide hands-on leadership for complex DFT implementations, incl. Scan Architecture, ATPG patterns and coverage analysis.
• Collaborate with Test Engineering and ATE teams to optimize test flows and yield improvements.
• Familiar with Functional Safety standards; guide DFT strategies to meet safety and diagnostic coverage goals.

Skills

Verilog

SystemVerilog

Python scripting

AI/LLM for DFT

Technical communication

Debugging & problem-solving

Education

Electrical / Electronic Engineering degree

Tools

SpyGlassDFT

IEEE 1149.1 (JTAG)

IJTAG (IEEE 1687)

Job description

Job Details: Job Description:

Key Responsibilities

DFT Architecture & Strategy Leadership

• Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms
• Drive DFT requirements at architecture and RTL definition stages, influencing design trade-offs early
• Own DFT methodology evolution, including scalability, reuse, and long-term roadmap alignment
• Lead design reviews and collaborate with stakeholders to drive closure

Advanced DFT Implementation & Sign-Off

• Provide hands-on leadership for complex DFT implementations, including but not limited to Scan Architecture, Scan Insertion, ATPG pattern generation and coverage analysis, Cell-Aware, Power Aware, Memory BIST and Repair, Streaming Scan Network (SSN), ICL extraction & PDL retargeting, etc.
• Strong knowledge on industrial test standards IEEE 1149.1 (JTAG) and/or IEEE 1687 (IJTAG)
• Drive DFT sign-off quality using tools such as SpyGlassDFT or equivalent
• Resolve complex testability, clocking, and reset challenges across large designs

Timing, Physical Design & Power

• Define and review DFT-related timing constraints across multiple clock domains
• Partner with front end & physical design teams to achieve timing closure for scan and test logic
• Address congestion, clock integrity, and DFT test-mode issues
• Lead DFT improvement strategies in timing & power optimization strategies and low-power DFT solutions

Post-silicon, Yield & Manufacturing Excellence

• Lead DFT design to collaborate with post-silicon team on silicon power on, debug, failure analysis, yield improvement initiatives using silicon learning and test data
• Support the initiatives of test cost optimization, coverage improvement, and DFT test hole reduction from system to tester
• Collaborate deeply with Test Engineering and ATE teams, influencing tester strategies, test hardware design and flows

Functional Safety & Quality

• Familiar with industrial Functional Safety standards to provide leadership in Functional Safety design related DFT strategies
• Define & drive the DFT implementation to support diagnostic coverage, safety mechanisms, and compliance goals
• Review and guide safety-related test concepts and documentation

Technical Leadership & Mentorship

• Mentor and guide Senior and Junior DFT engineers
• Set technical standards, review implementations, and raise overall DFT quality
• Act as a go-to expert for complex DFT and test-ability issues across teams
• Influence stakeholders across design, validation, manufacturing, and program management

Qualifications: Required Qualifications

• Bachelor’s or Master’s degree in Electrical / Electronic Engineering or related field
• 10+ years of industry experience in DFT design, with significant hands-on ownership
• Strong experience in DFT methodology, architecture & design in custom design blocks & PNR flows
• Proven ability to drive collaboration across architecture, RTL, PD, test, and manufacturing teams
• Strong Verilog and/or SystemVerilog proficiency
• Excellent technical communication and decision-making skills
• Good debugging, problem-solving, and communication skills
• Proven track record in driving AI or LLM to simplify or enhance DFT implementations in FPGA or SOC design

Preferred / Differentiating Qualifications

• Demonstrated leadership in DFT architecture definition for large or complex FPGA & SOC designs
• Strong experience with post-silicon debug, yield ramp, and production issues
• Hands-on exposure to industrial ATE platforms and tester limitations
• Hands-on experience in DFT design verification is a plus
• Experience driving DFT methodologies, flow development, or infrastructure improvements
• Expertise in low-power DFT and test power management
• Scripting and automation skills (Python, Tcl, Perl)
• Experience influencing multi-site or global teams

Job Type

Regular

Shift: Shift 1 (Malaysia)

Primary Location: Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.