Senior DFT Architect for FPGA & SoC Test

Altera; George Town; On-site; MYR 180,000 - 360,000; Full time

Job summary

Altera in Malaysia is seeking a senior DFT Architect to lead end-to-end DFT strategy for complex FPGA designs. You will drive architecture, RTL, and testability decisions, mentor engineers, and align DFT with safety and manufacturing goals.

The role requires 10+ years in DFT, strong Verilog/SystemVerilog skills, and experience with AI/LLM-assisted DFT improvements. Join a global team delivering scalable, high-quality test solutions.

Qualifications

• Bachelor’s or Master’s degree in Electrical / Electronic Engineering or related field.
• 10+ years of industry experience in DFT design with hands-on ownership.
• Strong experience in DFT methodology, architecture & design in custom design blocks & PNR flows.
• Proven ability to drive collaboration across architecture, RTL, PD, test, and manufacturing teams.
• Strong Verilog and/or SystemVerilog proficiency.
• Excellent technical communication and decision-making skills.
• Good debugging, problem-solving, and communication skills.
• Proven track record in driving AI or LLM to simplify or enhance DFT implementations in FPGA or SOC design.

Responsibilities

• Define end-to-end DFT architecture and strategy for FPGA designs and platforms.
• Drive DFT requirements at architecture and RTL definition stages, influencing design trade-offs early.
• Own DFT methodology evolution, including scalability, reuse, and long-term roadmap alignment.
• Lead design reviews and collaborate with stakeholders to drive closure.
• Provide hands-on leadership for complex DFT implementations, incl. Scan Architecture, ATPG patterns and coverage analysis.
• Collaborate with Test Engineering and ATE teams to optimize test flows and yield improvements.
• Familiar with Functional Safety standards; guide DFT strategies to meet safety and diagnostic coverage goals.

Skills

Verilog

SystemVerilog

Python scripting

AI/LLM for DFT

Technical communication

Debugging & problem-solving

Education

Electrical / Electronic Engineering degree

Tools

SpyGlassDFT

IEEE 1149.1 (JTAG)

IJTAG (IEEE 1687)

Job description

Altera in Malaysia is seeking a senior DFT Architect to lead end-to-end DFT strategy for complex FPGA designs. You will drive architecture, RTL, and testability decisions, mentor engineers, and align DFT with safety and manufacturing goals.

The role requires 10+ years in DFT, strong Verilog/SystemVerilog skills, and experience with AI/LLM-assisted DFT improvements. Join a global team delivering scalable, high-quality test solutions.