Hybrid FPGA/ASIC RTL Design Engineer - Verilog

Intel Corporation; George Town; Hybrid; MYR 80,000 - 110,000; Full time

Job summary

A leading technology company in Malaysia is seeking an experienced RTL designer to develop and maintain designs using Verilog/System Verilog for FPGA and ASIC solutions. The ideal candidate will have over 5 years of RTL/Logic design experience and knowledge in packet-based protocols. Strong analytical and problem-solving skills are essential. This role offers a hybrid work model, allowing employees to split their time between on-site and remote work.

Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog.
• Experience with Packet Based Protocols such as PCIe, USB, SPI, I2C is an advantage.
• Strong communication and teamwork skills.

Responsibilities

• Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions.
• Debug and resolve design and simulation issues.
• Ensure high design quality by following coding standards.

Skills

Verilog/System Verilog

Problem solving

Analytical ability

Communication

Teamwork

Tools

Quartus

Vivado

Logic analyzers

Scopes

Protocol analyzers

Job description

A leading technology company in Malaysia is seeking an experienced RTL designer to develop and maintain designs using Verilog/System Verilog for FPGA and ASIC solutions. The ideal candidate will have over 5 years of RTL/Logic design experience and knowledge in packet-based protocols. Strong analytical and problem-solving skills are essential. This role offers a hybrid work model, allowing employees to split their time between on-site and remote work.