ASIC/FPGA Design Engineer

Intel Corporation; George Town; On-site; MYR 80,000 - 110,000; Full time

Job summary

A leading technology company in Malaysia is seeking an experienced RTL designer to develop and maintain designs using Verilog/System Verilog for FPGA and ASIC solutions. The ideal candidate will have over 5 years of RTL/Logic design experience and knowledge in packet-based protocols. Strong analytical and problem-solving skills are essential. This role offers a hybrid work model, allowing employees to split their time between on-site and remote work.

Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog.
• Experience with Packet Based Protocols such as PCIe, USB, SPI, I2C is an advantage.
• Strong communication and teamwork skills.

Responsibilities

• Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions.
• Debug and resolve design and simulation issues.
• Ensure high design quality by following coding standards.

Skills

Verilog/System Verilog

Problem solving

Analytical ability

Communication

Teamwork

Tools

Quartus

Vivado

Logic analyzers

Scopes

Protocol analyzers

Job description

Job Details

Job Description:

• Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.
• Debug and resolve design and simulation issues, collaborate closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring‑up, and issue resolution.
• Ensure high design quality by following coding standards and maintaining proper technical documentation.

Qualifications

Minimum qualifications are required to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog RTL coding.

Preferred Qualifications

• Experience with Packet Based Protocols such as PCIe, USB, SPI, I2C and etc is an advantage.
• Experience in agentic AI is an advantage.
• Demonstrable experience in logic design and writing RTL in Verilog or System Verilog.
• Familiarity with a range of internal and 3rd‑party logic design tools.
• Strong analytical ability, problem solving and communication skills.
• Gate‑level understanding of RTL and synthesis – i.e. understand how RTL looks like/behaves after it is synthesized into gates.
• Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues.
• Strong communication and teamwork still.
• Ability to work independently and at various levels of abstraction.
• Ability to lead a team of designer.
• Knowledge in FPGA design and debug with FPGA tools like Quartus/Vivado will be an added advantage.
• Knowledge on embedded SW which using NIOS or ARM processor is an added advantage.
• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type

Experienced Hire

Shift

Shift 1 (Malaysia)

Primary Location

Malaysia, Penang

Business Group

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry‑leading products today while also defining the next generation of computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.