Senior FPGA/ASIC Design Engineer - Hybrid, Lead & RTL

Intel Corporation; Penang; Hybrid; MYR 80,000 - 120,000; Full time

Job summary

A leading semiconductor company in Malaysia seeks an experienced ASIC/FPGA Design Engineer to develop and maintain RTL designs using Verilog/System Verilog. Candidates should have 5+ years in RTL/Logic design, strong analytical and problem-solving skills, and the ability to collaborate effectively with cross-functional teams. Knowledge of guidelines and coding standards is essential, alongside familiarity with tools like Quartus and Vivado. The role offers a hybrid work model, balancing on-site and off-site work.

Qualifications

• 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or System Verilog.
• Experience with Packet Based Protocols such as PCIe, USB, SPI, and I2C.
• Familiarity with internal and third-party logic design tools.

Responsibilities

• Develop and maintain RTL designs using Verilog/System Verilog.
• Perform functional simulation and verification.
• Collaborate closely with architects and verification engineers.

Skills

RTL/Logic design

Verilog/System Verilog

Analytical ability

Problem solving

Communication skills

Teamwork

Tools

Quartus

Vivado

Logic analyzers

Protocol analyzers

Job description

A leading semiconductor company in Malaysia seeks an experienced ASIC/FPGA Design Engineer to develop and maintain RTL designs using Verilog/System Verilog. Candidates should have 5+ years in RTL/Logic design, strong analytical and problem-solving skills, and the ability to collaborate effectively with cross-functional teams. Knowledge of guidelines and coding standards is essential, alongside familiarity with tools like Quartus and Vivado. The role offers a hybrid work model, balancing on-site and off-site work.