FPGA/SoC Timing Engineer - Signoff & Closure

Altera; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera invites a SOC Timing Engineer in Penang to own timing closure for FPGA/SoC and subsystems. You will perform static timing analysis, derive interface timing constraints, and drive final timing signoff. You will collaborate with design, architecture and physical design teams to converge timing and meet 10nm or lower tapeout readiness.

Candidates should have strong communication and analytical skills. Regular full-time role based in Penang with a shift 1 Malaysia.

Qualifications

• Experience in static timing analysis and signoff using industry tools.
• Good understanding of timing constraints, clocking and PVT variations.
• Tapeout experience including latest technology 10nm or lower.
• 3+ years in physical design with timing closure and signoff.

Responsibilities

• Own timing closure and signoff for FPGA/SoC and subsystems.
• Perform static timing analysis and derive interface timing constraints.
• Converge timing with design and architecture teams and coordinate with physical design.
• Support timing signoff through final verification with cross-functional teams.

Skills

Static timing analysis

Timing constraints & clocking

PVT understanding

Physical design timing closure

Education

BE/MS/PhD in Electronics/Electrical Engineering

Tools

Primetime/PTPX

Job description

Altera invites a SOC Timing Engineer in Penang to own timing closure for FPGA/SoC and subsystems. You will perform static timing analysis, derive interface timing constraints, and drive final timing signoff. You will collaborate with design, architecture and physical design teams to converge timing and meet 10nm or lower tapeout readiness.

Candidates should have strong communication and analytical skills. Regular full-time role based in Penang with a shift 1 Malaysia.