SOC Timing Engineer

Altera; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera invites a SOC Timing Engineer in Penang to own timing closure for FPGA/SoC and subsystems. You will perform static timing analysis, derive interface timing constraints, and drive final timing signoff. You will collaborate with design, architecture and physical design teams to converge timing and meet 10nm or lower tapeout readiness.

Candidates should have strong communication and analytical skills. Regular full-time role based in Penang with a shift 1 Malaysia.

Qualifications

• Experience in static timing analysis and signoff using industry tools.
• Good understanding of timing constraints, clocking and PVT variations.
• Tapeout experience including latest technology 10nm or lower.
• 3+ years in physical design with timing closure and signoff.

Responsibilities

• Own timing closure and signoff for FPGA/SoC and subsystems.
• Perform static timing analysis and derive interface timing constraints.
• Converge timing with design and architecture teams and coordinate with physical design.
• Support timing signoff through final verification with cross-functional teams.

Skills

Static timing analysis

Timing constraints & clocking

PVT understanding

Physical design timing closure

Education

BE/MS/PhD in Electronics/Electrical Engineering

Tools

Primetime/PTPX

Job description

## SOC Timing EngineerApplylocations: Penang 15, Penang, Malaysiatime type: Full timeposted on: Posted Todayjob requisition id: R02767# **Job Details:**### ## **Job Description:*** As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.* Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.* Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure### ## **Qualifications:**Experience in Static timing analysis , and industry standard EDA tools like Primetime/PTPX- Good understanding of timing constraints, clocking, PVT etc- Should have tapeout experience including in latest technology 10nm or lower- BE/MS/Phd in Electronics/Electrical Engineering with 3+ Years' experience in physical design and timing closure/signoff-Candidate should be strong in communication, problem solving and analytical skill### ## **Job Type:**Regular### ## **Shift:**Shift 1 (Malaysia)### ## **Primary Location:**Penang 15, Penang, Malaysia### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**About Altera**Altera: Accelerating InnovatorsAltera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.