Senior Digital IC Design Engineer – NoC & SoC RTL

Career International 科锐国际; Bayan Lepas; On-site; MYR 150,000 - 210,000; Full time

Job summary

Career International 科锐国际 in Penang, Malaysia, seeks a senior IC/SoC design engineer to design and develop digital IP and NoC interconnect architectures. The role focuses on RTL/Verilog implementation and interconnect optimization.

You will work with architecture, verification and physical design teams to ensure correct silicon delivery, with expertise in AXI/AMBA/PCIe protocols and complex digital logic. 8–10 years experience preferred.

Qualifications

• Master's degree required in a relevant engineering field.
• Minimum 8 years of hands-on digital IC/SoC design experience.
• Strong proficiency in Verilog/SystemVerilog and RTL implementation.

Responsibilities

• Design and develop digital IP and SoC interconnect architectures including NoC components.
• Define microarchitecture and RTL using Verilog/SystemVerilog.
• Develop interconnect functionality: topology, routing, arbitration, QoS.
• Support integration with processors, accelerators, and memory controllers.
• Collaborate with architecture, design verification and physical design teams for correctness and implementation.
• Perform performance analysis and optimization for bandwidth, latency, power, and area.
• Support synthesis, timing analysis, design reviews, debugging and silicon delivery.
• Contribute to engineering best practices as the team grows.

Skills

Digital IC design

Verilog/SystemVerilog

RTL design

IP architecture

SoC interconnect

AXI/AMBA/PCIe

Education

Master's degree in Microelectronics, Electrical/Electronic Engineering, Integrated Circuits, Computer Engineering or related

Job description

Career International 科锐国际 in Penang, Malaysia, seeks a senior IC/SoC design engineer to design and develop digital IP and NoC interconnect architectures. The role focuses on RTL/Verilog implementation and interconnect optimization.

You will work with architecture, verification and physical design teams to ensure correct silicon delivery, with expertise in AXI/AMBA/PCIe protocols and complex digital logic. 8–10 years experience preferred.