DFT (Design-for-Test) Engineer

Pride Global; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Pride Global is seeking an experienced Design-for-Test (DFT) Engineer in Penang to work on cutting-edge ASIC/SoC projects. You will develop and implement DFT solutions to ensure high test coverage and robust silicon validation.

The role requires 4+ years in ASIC/SoC DFT, RTL/design understanding, and proficiency with Synopsys DFT tools. Collaboration with global teams and automation scripting are essential to success.

Qualifications

• 4+ years of hands-on ASIC/SoC DFT experience.
• Strong RTL design understanding and synthesis.
• Experience with Synopsys Design Compiler, DFTMAX, TetraMAX, Fusion Compiler.
• Scripting in Tcl, Python, or Perl.
• Experience with silicon validation, ATE, yield analysis is a plus.

Responsibilities

• Define and implement chip-level DFT architecture and test strategies.
• Integrate MBIST, LBIST, JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and IEEE 1500 test structures.
• Generate and optimize ATPG patterns for fault models.
• Perform RTL and gate-level verification of DFT implementation.
• Collaborate with product teams during silicon bring-up, debugging, and yield improvement.
• Develop automation scripts to streamline DFT flows.

Skills

ASIC/SoC DFT expertise

RTL design understanding

Digital design fundamentals

Synthesis knowledge

Tcl

Python

Perl

Automation scripting

Education

Bachelor's/Master's in EE/CE

Tools

Synopsys Design Compiler

Synopsys DFTMAX

Synopsys TetraMAX

Synopsys Fusion Compiler

Job description

Eligibility: Only Malaysian Citizens, PR or RPT holders

Employment Type: Full-time

Are you passionate about semiconductor design and advanced ASIC/SoC development? We're partnering with a leading global technology company to hire experienced Design-for-Test (DFT) Engineers who are eager to work on cutting-edge silicon technologies and next-generation chip designs.

In this role, you'll be responsible for developing and implementing DFT solutions that ensure high manufacturing quality, optimal test coverage, and efficient silicon validation for complex SoCs.

Key Responsibilities

• Define and implement chip-level DFT architecture and test strategies.
• Integrate scan compression, MBIST, LBIST, JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and IEEE 1500 test structures.
• Generate and optimize ATPG patterns for various fault models, including stuck-at, transition delay, and cell-aware faults.
• Perform RTL and gate-level verification of DFT implementation and support pre-/post-layout DFT validation.
• Collaborate with product engineering teams during silicon bring-up, debugging, and yield improvement activities.
• Develop automation scripts to streamline DFT flows and improve engineering productivity.

Key Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 4+ years of hands-on experience in ASIC/SoC Design-for-Test (DFT).
• Strong understanding of RTL design, digital design fundamentals, and synthesis.
• Experience with one or more of the following EDA tool suites:
• Synopsys: Design Compiler, DFTMAX, TetraMAX, Fusion Compiler
• Proficiency in scripting languages such as Tcl, Python, or Perl.
• Experience with silicon validation, ATE, and yield analysis is an added advantage.

Why Apply?

• Join a leading organization driving innovation in advanced semiconductor technologies.
• Work on complex ASIC/SoC projects using industry-leading EDA tools.
• Collaborate with highly skilled global engineering teams.
• Competitive compensation, excellent career growth opportunities, and exposure to next-generation chip development.