DFX Design Architect

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 150,000 - 200,000; Full time

Job summary

754 Altera Semiconductor Technology (M) Sdn. Bhd. is hiring a DFX Architect in Penang, Malaysia. This role requires defining the strategy for Design for Test (DFT) and Design for Debug (DFD) on next-generation FPGA and SoC families.

The ideal candidate will have over 10 years of experience, particularly in DFT/DFD, and will drive the adoption of new technologies. The position offers a regular shift in a dynamic work environment, focusing on advanced semiconductor designs.

Qualifications

• Minimum 10–12 years of hands-on experience in DFT/DFD.
• Experience in architectural roles and semiconductor product life cycle.
• Deep expertise in Hierarchical DFT and established DFT standards.

Responsibilities

• Define and document DFX architectures for multi-die systems.
• Drive adoption of advanced DFX features.
• Lead definition of on-chip debug infrastructures.

Skills

DFT/DFD expertise

Leadership & Strategic thinking

Silicon Debug

Advanced DFT Concepts

Scripting in Tcl/Python

Education

BS/MS or Ph.D. in Electrical/Electronics/Computer Engineering

Tools

Tessent (Siemens)

DesignCompiler/DFTMAX (Synopsys)

Job description

DFX Architect

As a DFX Architect, you will be the technical authority for Altera’s next‑generation FPGA and SoC families, defining the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world‑class quality, minimize Test Cost (TCO), and accelerate Time‑to‑Market (TTM).

Key Responsibilities

• Architectural Strategy: Define and document DFX architectures for multi‑die (chiplet) systems, high‑speed transceivers, and massive FPGA fabrics.
• Technology Leadership: Drive the adoption of advanced DFX features such as IEEE 1687 (IJTAG), IEEE 1838 (3D‑IC), and High‑Speed Link Testing (HSLT).
• Test Cost Optimization: Develop strategies to reduce Test Data Volume (TDV) and Test Application Time (TAT) through advanced compression and adaptive testing techniques.
• Debug Architecture: Lead the definition of on‑chip debug infrastructures (logic analyzers, trace buffers, and scan‑dump) to enable rapid root‑cause analysis of complex silicon failures.
• Cross‑Functional Influence: Partner with Silicon Design Architects, Manufacturing and Post‑Silicon System Debug experts to ensure DFT and DFD feature requirements are baked into the hardware specifications as landing zone features.
• Tool & Flow Roadmap: Influence EDA vendors (Synopsys, Siemens/Mentor, Cadence) to align their roadmaps with Altera’s specific FPGA architectural needs.
• Mentorship: Act as a technical beacon for the Penang engineering site, mentoring senior and staff engineers.

Qualifications

• Education: BS/MS or Ph.D. in Electrical/Electronics/Computer Engineering or a related field.
• Experience: Minimum 10–12 years of hands‑on experience in DFT/DFD, with at least 4 years in an architectural or lead capacity; familiarity with the semiconductor end‑to‑end product life cycle for ASIC and FPGA.
• Advanced DFT Concepts: Deep expertise in Hierarchical DFT, Logic/Mem BIST, Scan Compression (EDT), Boundary Scan, JTAG/iJTAG and other established DFT standards.
• Multi‑Die/Chiplet Knowledge: Experience with 2.5D/3D packaging technologies and the specific DFX challenges associated with interposers and TSVs.
• Silicon Debug: Expert knowledge of silicon bring‑up, failure analysis, and the use of DFD hooks for in‑system hardware/firmware co‑debugging.
• FPGA Architecture (Highly Preferred): Specific understanding of FPGA‑specific testing, e.g., configuration RAM testing and programmable interconnect verification.
• Safety Standards: Proven experience designing DFX architectures that meet ASIL‑D and other industrial functional safety standard requirements.
• EDA & Tool Standards: Proficiency in Tessent (Siemens), DesignCompiler/DFTMAX (Synopsys), or equivalent suites; deep familiarity with IEEE standards (1149.1, 1149.6, 1500, 1687, 1838); scripting in Tcl/Python for custom tools.
• Leadership & Soft Skills: Strategic thinking, stakeholder management, problem solving.

Job Type & Location

Regular Shift: Shift 1 (Malaysia)

Primary Location: Penang, Malaysia

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.