DFT Architect — ASIC/SoC Test & Automation

Pride Global; Penang; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global in Penang is seeking an experienced Design-for-Test (DFT) Engineer to develop and implement DFT solutions for high-performance ASICs and SoCs. The role focuses on delivering high test coverage, reduced test cost, and efficient test execution while preserving PPA targets.

Responsibilities include defining DFT architectures, test strategies, and integration of scan compression with leading EDA tools. Collaboration with product engineering teams is essential.

Qualifications

• BS or MS in EE/CE or related field.
• 4–15 years of ASIC/SoC DFT experience.
• Proficiency in Verilog/SystemVerilog/VHDL and SDA synthesis.
• Experience with production DFT flows and ATPG required.

Responsibilities

• Define and implement chip-level DFT architecture (scan, MBIST/LBIST, JTAG).
• Develop test strategies, clock/reset architectures and DFT specs.
• Integrate scan compression using industry EDA tools (DFTMAX, Tessent, Modus).
• Generate ATPG patterns for Stuck-at, TDL, Cell-Aware, Path Delay models.
• Verify DFT via RTL and gate-level simulations; pre/post-layout validation.
• Support silicon bring-up, ATE debugging, yield improvement with teams.

Skills

Verilog/SystemVerilog/VHDL

Digital design

Synthesis

ATPG

Tcl scripting

Python scripting

Perl scripting

Education

Bachelor's or Master's degree in Electrical or Computer Engineering

Tools

Synopsys DFTMAX

Siemens Tessent

Cadence Modus

Cadence Genus

Job description

Pride Global in Penang is seeking an experienced Design-for-Test (DFT) Engineer to develop and implement DFT solutions for high-performance ASICs and SoCs. The role focuses on delivering high test coverage, reduced test cost, and efficient test execution while preserving PPA targets.

Responsibilities include defining DFT architectures, test strategies, and integration of scan compression with leading EDA tools. Collaboration with product engineering teams is essential.