DFX Design Architect

Altera; Bayan Lepas; On-site; MYR 250,000 - 420,000; Full time

Job summary

Altera in Penang seeks a DFX Architect to lead design-for-test and design-for-debug strategies for next‑generation FPGA and SoC families. You will define architectures, drive DFX features, and collaborate with silicon, physical design, and post‑silicon teams across global sites to ensure world‑class quality and rapid time‑to‑market.

In this high‑visibility role, you will mentor engineers, influence EDA tool roadmaps, and balance test coverage with die area constraints while adhering to

Qualifications

• 10–12 years hands‑on DFT/DFD experience, with at least 4 years in a lead/architect role.
• Deep expertise in Hierarchical DFT, Logic/Memory BIST, Scan Compression (EDT) and Boundary Scan (JTAG/iJTAG).
• Experience with 2.5D/3D packaging and interposers/TSVs.
• Silicon bring‑up, failure analysis, and in‑system hardware/firmware co‑debugging.

Responsibilities

• Define and document DFX architectures for multi‑die systems and FPGA fabrics.
• Drive adoption of IEEE 1687 (IJTAG), 1838 (3D‑IC), and high‑speed link testing techniques.
• Develop strategies to reduce Test Data Volume and Test Application Time via compression and adaptive testing.
• Lead on‑chip debug infrastructure design (logic analyzers, trace buffers, scan‑dump).
• Collaborate with Silicon Design, Manufacturing and Post‑Silicon Debug to bake DFT/DFD features into hardware specs.
• Influence EDA roadmaps to meet Altera’s FPGA architectural needs.
• Mentor Penang engineers to raise the site’s technical depth.

Skills

DFT/DFD architecture

Hierarchical DFT

JTAG/iJTAG

FPGA architecture knowledge

Silicon debug

Problem solving

Stakeholder management

Education

BS/MS/PhD in Electrical/Electronics/Computer Engineering

Tools

Tessent (Siemens)

DesignCompiler/DFTMAX (Synopsys)

Tcl/Python scripting

Job description

Job Description

As a DFX Architect, you will be the technical authority for Altera’s next-generation FPGA and SoC families. You will define the overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world‑class quality, minimize Test Cost (TCO), and accelerate Time‑to‑Market (TTM). This high‑visibility leadership role requires collaboration with Silicon Architecture, Physical Design, and Post‑Silicon Manufacturing teams across global sites.

Key Responsibilities

• Architectural Strategy: Define and document DFX architectures for multi‑die (chiplet) systems, high‑speed transceivers, and massive FPGA fabrics.
• Technology Leadership: Drive the adoption of advanced DFX features such as IEEE 1687 (IJTAG), IEEE 1838 (3D‑IC), and High‑Speed Link Testing (HSLT).
• Test Cost Optimization: Develop strategies to reduce Test Data Volume (TDV) and Test Application Time (TAT) through advanced compression and adaptive testing techniques.
• Debug Architecture: Lead the definition of on‑chip debug infrastructures (e.g., logic analyzers, trace buffers, and scan‑dump) to enable rapid root‑cause analysis of complex silicon failures.
• Cross‑Functional Influence: Partner with Silicon Design Architects, Manufacturing and Post‑Silicon System Debug experts to drive DFT and DFD feature requirements that are baked into the hardware specifications as landing zone features.
• Tool & Flow Roadmap: Influence EDA vendors (Synopsys, Siemens/Mentor, Cadence) so that their roadmaps align with Altera’s specific FPGA architectural needs.
• Mentorship: Act as a technical beacon for the Penang engineering site, mentoring senior and staff engineers to elevate the organization’s technical depth.

Qualifications

Education

• BS / MS or Ph.D. in Electrical/Electronics/Computer Engineering or a related field.

Technical Requirements

• Proven Track Record: Minimum 10‑12 years of hands‑on experience in DFT/DFD, with at least 4 years in an architectural or lead capacity. Familiar with the semiconductor end‑to‑end product life cycle for ASIC and FPGA.
• Advanced DFT Concepts: Deep expertise in Hierarchical DFT, Logic/Memory BIST, Scan Compression (EDT), Boundary Scan, JTAG/iJTAG and other established DFT standards.
• Multi‑Die/Chiplet Knowledge: Experience with 2.5D/3D packaging technologies and the specific DFX challenges associated with interposers and TSVs.
• Silicon Debug: Expert knowledge of silicon bring‑up, failure analysis, and the use of DFD hooks for in‑system hardware/firmware co‑debugging.
• FPGA Architecture: (Highly Preferred) Specific understanding of FPGA‑specific testing, such as configuration RAM testing and programmable interconnect verification.
• Safety Standards: Proven experience in designing DFX architectures that meet ASIL‑D (Automotive Safety Integrity Level) and other industrial functional safety standards for semiconductor products.

EDA & Tool Standards

• Expertise in Tessent (Siemens), DesignCompiler/DFTMAX (Synopsys), or equivalent industry‑leading suites.
• Deep familiarity with IEEE standards (1149.1, 1149.6, 1500, 1687, 1838).
• Proficiency in scripting (Tcl/Python) to build custom architectural modeling or validation tools.

Leadership & Soft Skills

• Strategic Thinking: Ability to balance technical perfection with business constraints (die area overhead vs. test coverage).
• Stakeholder Management: Experience presenting complex technical roadmaps to executive leadership and global stakeholders.
• Problem Solving: A reputation for resolving mission‑critical silicon issues that bridge design and manufacturing.

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location

Penang 15, Penang, Malaysia

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.