DFT Engineer

Pride Global; Penang; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global in Penang is seeking an experienced Design-for-Test (DFT) Engineer to develop and implement DFT solutions for high-performance ASICs and SoCs. The role focuses on delivering high test coverage, reduced test cost, and efficient test execution while preserving PPA targets.

Responsibilities include defining DFT architectures, test strategies, and integration of scan compression with leading EDA tools. Collaboration with product engineering teams is essential.

Qualifications

• BS or MS in EE/CE or related field.
• 4–15 years of ASIC/SoC DFT experience.
• Proficiency in Verilog/SystemVerilog/VHDL and SDA synthesis.
• Experience with production DFT flows and ATPG required.

Responsibilities

• Define and implement chip-level DFT architecture (scan, MBIST/LBIST, JTAG).
• Develop test strategies, clock/reset architectures and DFT specs.
• Integrate scan compression using industry EDA tools (DFTMAX, Tessent, Modus).
• Generate ATPG patterns for Stuck-at, TDL, Cell-Aware, Path Delay models.
• Verify DFT via RTL and gate-level simulations; pre/post-layout validation.
• Support silicon bring-up, ATE debugging, yield improvement with teams.

Skills

Verilog/SystemVerilog/VHDL

Digital design

Synthesis

ATPG

Tcl scripting

Python scripting

Perl scripting

Education

Bachelor's or Master's degree in Electrical or Computer Engineering

Tools

Synopsys DFTMAX

Siemens Tessent

Cadence Modus

Cadence Genus

Job description

Employment type : Open to Perm & Contract

Working arrangement : Onsite

Salary Range : 4 – 6 Years (11-12k), 6 – 8 Years (13-15k), 8 – 10 Years (16-18k)

Position Overview

We are seeking an experienced Design-for-Test (DFT) Engineer to develop and implement DFT solutions for high-performance ASICs and SoCs. The role focuses on delivering high manufacturing test coverage, optimized test cost, and efficient test execution while maintaining power, performance, and area (PPA) targets.

Key Responsibilities

• Define and implement chip-level DFT architecture, including scan, MBIST, LBIST, JTAG, IJTAG, and IEEE 1500 wrapper chains.
• Develop test strategies, clock/reset architectures, and DFT specifications for complex SoCs.
• Integrate scan compression solutions using industry-standard EDA tools (Synopsys DFTMAX, Siemens Tessent, Cadence Modus).
• Generate and optimize ATPG patterns for Stuck-at, Transition Delay, Cell-Aware, and Path Delay fault models.
• Verify DFT implementation through RTL and gate-level simulations, and perform pre- and post-layout DFT validation.
• Support silicon bring-up, ATE debugging, failure analysis, and yield improvement in collaboration with product engineering teams.
• Develop automation scripts using Tcl, Python, or Perl to improve DFT flow efficiency.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 4–15 years of hands-on experience in ASIC/SoC DFT implementation.
• Strong knowledge of Verilog/SystemVerilog/VHDL, digital design, and synthesis.
• Hands-on experience with Synopsys (Design Compiler, DFTMAX, TetraMAX, Fusion Compiler), Siemens Tessent/FastScan/TestKompress, or Cadence Modus/Genus.
• Proficiency in Tcl, Python, or Perl scripting for automation.
• Experience with production DFT flows, ATPG, scan insertion, MBIST/LBIST, and silicon debug is highly preferred.