DFX Architect: FPGA/SoC Debug & Test Strategy

Altera; Bayan Lepas; On-site; MYR 250,000 - 420,000; Full time

Job summary

Altera in Penang seeks a DFX Architect to lead design-for-test and design-for-debug strategies for next‑generation FPGA and SoC families. You will define architectures, drive DFX features, and collaborate with silicon, physical design, and post‑silicon teams across global sites to ensure world‑class quality and rapid time‑to‑market.

In this high‑visibility role, you will mentor engineers, influence EDA tool roadmaps, and balance test coverage with die area constraints while adhering to

Qualifications

• 10–12 years hands‑on DFT/DFD experience, with at least 4 years in a lead/architect role.
• Deep expertise in Hierarchical DFT, Logic/Memory BIST, Scan Compression (EDT) and Boundary Scan (JTAG/iJTAG).
• Experience with 2.5D/3D packaging and interposers/TSVs.
• Silicon bring‑up, failure analysis, and in‑system hardware/firmware co‑debugging.

Responsibilities

• Define and document DFX architectures for multi‑die systems and FPGA fabrics.
• Drive adoption of IEEE 1687 (IJTAG), 1838 (3D‑IC), and high‑speed link testing techniques.
• Develop strategies to reduce Test Data Volume and Test Application Time via compression and adaptive testing.
• Lead on‑chip debug infrastructure design (logic analyzers, trace buffers, scan‑dump).
• Collaborate with Silicon Design, Manufacturing and Post‑Silicon Debug to bake DFT/DFD features into hardware specs.
• Influence EDA roadmaps to meet Altera’s FPGA architectural needs.
• Mentor Penang engineers to raise the site’s technical depth.

Skills

DFT/DFD architecture

Hierarchical DFT

JTAG/iJTAG

FPGA architecture knowledge

Silicon debug

Problem solving

Stakeholder management

Education

BS/MS/PhD in Electrical/Electronics/Computer Engineering

Tools

Tessent (Siemens)

DesignCompiler/DFTMAX (Synopsys)

Tcl/Python scripting

Job description

Altera in Penang seeks a DFX Architect to lead design-for-test and design-for-debug strategies for next‑generation FPGA and SoC families. You will define architectures, drive DFX features, and collaborate with silicon, physical design, and post‑silicon teams across global sites to ensure world‑class quality and rapid time‑to‑market.

In this high‑visibility role, you will mentor engineers, influence EDA tool roadmaps, and balance test coverage with die area constraints while adhering to