Design Verification Engineer

Axcellence Consulting; George Town; On-site; MYR 100,000 - 180,000; Full time

Job summary

Axcellence Consulting in Penang, Malaysia is seeking a senior RTL Engineer to develop, verify, and optimize ASIC/SoC RTL designs using Verilog/SystemVerilog. You will contribute to architecture, microarchitecture, RTL implementation, and system integration.

You will build UVM-based verification environments, write SVAs, and create functional coverage models, while debugging issues across IP to SoC levels. The role emphasizes applying Generative AI and agentic tooling to boost productivity and

Qualifications

• Bachelor's degree or higher in Electrical/Computer Engineering or CS.
• Minimum 3 years in ASIC/SoC RTL Design and/or Design Verification.
• At least 1 year applying AI/ML or Generative AI technologies.
• Strong proficiency in Verilog/SystemVerilog and RTL design methods.
• Solid understanding of ASIC/SoC flows, UVM verification, and SVA.
• Experience with Generative AI, LLMs, and AI agent workflows.
• Strong Python, Linux, Git, and scripting automation skills.
• Familiarity with MCP, LangChain, LangGraph, AutoGen, or CrewAI.
• Experience with cloud-based AI platforms and AI tooling.
• Strong analytical, problem-solving, and cross-functional collaboration skills.

Responsibilities

• Develop, maintain, and optimize RTL designs using Verilog/SystemVerilog for ASIC/SoC products.
• Contribute to architecture definition, microarchitecture development, RTL implementation, and system integration.
• Develop UVM-based verification environments, test plans, test cases, SVA, and functional coverage models.
• Debug functional, performance, and integration issues across IP, subsystem, and SoC levels.
• Design and develop AI agents and copilots to enhance RTL design, verification, debugging, code review, and productivity.
• Apply Generative AI, LLMs, and agentic AI technologies to automate RTL analysis, test plan and assertion generation, coverage analysis, and debug triage.
• Build AI-powered engineering workflows using Python, LangChain, MCP tools, vector databases, and GenAI platforms.
• Collaborate with cross-functional teams to identify and implement high-impact AI use cases.
• Drive AI adoption across silicon engineering teams by developing reusable frameworks, sharing best practices, and establishing methodologies.
• Mentor engineers in AI-assisted design and verification practices and evaluate productivity improvements.

Skills

Verilog

SystemVerilog

RTL Design

UVM

SVA

Python

Linux

Git

AI/ML

Generative AI

LangChain

MCP

RAG

Cloud Platforms

Education

Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science

Tools

UVM

SystemVerilog Assertions (SVA)

LangChain

LangGraph

AutoGen

CrewAI

MCP

RAG

Cloud AI Platforms

Job description

• Develop, maintain, and optimize RTL designs using Verilog/SystemVerilog for ASIC/SoC products.
• Contribute to architecture definition, microarchitecture development, RTL implementation, and system integration.
• Develop UVM-based verification environments, test plans, test cases, SystemVerilog Assertions (SVA), and functional coverage models.
• Debug functional, performance, and integration issues across IP, subsystem, and SoC levels.
• Design and develop AI agents and copilots to enhance RTL design, verification, debugging, code review, and engineering productivity.
• Apply Generative AI, Large Language Models (LLMs), and agentic AI technologies to automate RTL analysis, test plan and assertion generation, coverage analysis, debug triage, and regression failure root-cause analysis.
• Build AI-powered engineering workflows using Python, LangChain, MCP tools, vector databases, and modern GenAI platforms.
• Collaborate with cross-functional teams, including Architecture, Design, Design Verification (DV), Physical Design, Emulation, Post-Silicon, and Software Engineering, to identify and implement high-impact AI use cases.
• Drive AI adoption across silicon engineering teams by developing reusable frameworks, sharing best practices, and establishing effective methodologies.
• Mentor engineers in AI-assisted design and verification practices, and evaluate the productivity improvements achieved through AI-enabled solutions.

Requirements & Qualifications

• Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related discipline
• Minimum 3 years of experience in ASIC/SoC RTL Design and/or Design Verification.
• At least 1 year of hands-on experience applying AI/ML or Generative AI technologies.
• Strong proficiency in Verilog/SystemVerilog and RTL design methodologies.
• Solid understanding of ASIC/SoC development flows, UVM-based verification, functional coverage, and SystemVerilog Assertions (SVA).
• Practical experience with Generative AI, LLMs, prompt engineering, and AI agent workflows.
• Strong Python programming skills, with experience in Linux, Git, and scripting automation.
• Familiarity with Retrieval-Augmented Generation (RAG), Model Context Protocol (MCP), and AI development frameworks such as LangChain, LangGraph, AutoGen, or CrewAI.
• Familiarity with cloud-based AI platforms and AI-assisted software development tools.
• Strong analytical, problem-solving, and debugging skills.
• Excellent cross-functional communication and collaboration skills, with the ability to work effectively in multi-site teams and manage multiple priorities.