AI-Driven RTL Design & Verification Engineer

Risewave Consulting, Inc.; Bayan Lepas; On-site; MYR 120,000 - 240,000; Full time

Job summary

Risewave Consulting, Inc. is seeking an AI Silicon Design Engineer in Penang to advance RTL design and verification for ASIC/SoC products. You will blend Verilog/SystemVerilog expertise with AI/ML techniques to boost productivity and quality across the silicon lifecycle.

The role requires hands-on RTL development, UVM verification, and strong scripting skills in Python. You will collaborate with architecture, DV, physical design, and software teams to deliver high-impact AI-enabled workflows.

Qualifications

• 3+ years ASIC/SoC RTL design or verification
• 1+ year AI/ML or Generative AI experience
• Strong Verilog/SystemVerilog and RTL methodologies

Responsibilities

• Develop RTL in Verilog/SystemVerilog for ASIC/SoC products
• Participate in architecture definition, microarchitecture development, implementation, and integration
• Develop UVM-based verification environments, test plans, testcases, assertions, and coverage models
• Debug functional, performance, and integration issues across IP, subsystem, and SoC levels
• Develop AI agents and copilots to accelerate RTL design, verification, debug, code review, and productivity workflows
• Apply LLMs and Agentic AI technologies to automate tasks such as RTL understanding, test plan and assertion generation, coverage analysis, debug triage, and regression failure root‑cause analysis
• Build AI-powered engineering workflows using Python, LangChain, MCP, vector databases, and modern GenAI platforms
• Collaborate closely with Architecture, Design, DV, Physical Design, Emulation, Post‑Silicon, and Software teams to identify high‑impact AI use cases
• Drive AI adoption across silicon engineering teams; share best practices, methodologies, and reusable AI frameworks
• Mentor engineers on AI-assisted design and verification technologies, and measure/report productivity improvements enabled by AI solutions

Skills

ASIC/SoC RTL

AI/ML for eng

Python scripting

Verilog/SystemVerilog

UVM verification

Tools

LangChain

LangGraph

AutoGen

CrewAI

Git

Linux

Job description

Risewave Consulting, Inc. is seeking an AI Silicon Design Engineer in Penang to advance RTL design and verification for ASIC/SoC products. You will blend Verilog/SystemVerilog expertise with AI/ML techniques to boost productivity and quality across the silicon lifecycle.

The role requires hands-on RTL development, UVM verification, and strong scripting skills in Python. You will collaborate with architecture, DV, physical design, and software teams to deliver high-impact AI-enabled workflows.