Design Verification Engineer

Risewave Consulting, Inc.; Bayan Lepas; On-site; MYR 120,000 - 240,000; Full time

Job summary

Risewave Consulting, Inc. is seeking an AI Silicon Design Engineer in Penang to advance RTL design and verification for ASIC/SoC products. You will blend Verilog/SystemVerilog expertise with AI/ML techniques to boost productivity and quality across the silicon lifecycle.

The role requires hands-on RTL development, UVM verification, and strong scripting skills in Python. You will collaborate with architecture, DV, physical design, and software teams to deliver high-impact AI-enabled workflows.

Qualifications

• 3+ years ASIC/SoC RTL design or verification
• 1+ year AI/ML or Generative AI experience
• Strong Verilog/SystemVerilog and RTL methodologies

Responsibilities

• Develop RTL in Verilog/SystemVerilog for ASIC/SoC products
• Participate in architecture definition, microarchitecture development, implementation, and integration
• Develop UVM-based verification environments, test plans, testcases, assertions, and coverage models
• Debug functional, performance, and integration issues across IP, subsystem, and SoC levels
• Develop AI agents and copilots to accelerate RTL design, verification, debug, code review, and productivity workflows
• Apply LLMs and Agentic AI technologies to automate tasks such as RTL understanding, test plan and assertion generation, coverage analysis, debug triage, and regression failure root‑cause analysis
• Build AI-powered engineering workflows using Python, LangChain, MCP, vector databases, and modern GenAI platforms
• Collaborate closely with Architecture, Design, DV, Physical Design, Emulation, Post‑Silicon, and Software teams to identify high‑impact AI use cases
• Drive AI adoption across silicon engineering teams; share best practices, methodologies, and reusable AI frameworks
• Mentor engineers on AI-assisted design and verification technologies, and measure/report productivity improvements enabled by AI solutions

Skills

ASIC/SoC RTL

AI/ML for eng

Python scripting

Verilog/SystemVerilog

UVM verification

Tools

LangChain

LangGraph

AutoGen

CrewAI

Git

Linux

Job description

We are seeking a highly motivated AI Silicon Design Engineer to drive the next generation of AI-assisted silicon development. This role combines traditional RTL design and verification expertise with AI/ML technologies to improve engineering productivity, quality, and development efficiency across the silicon lifecycle. The ideal candidate has a solid foundation in ASIC/SoC design and verification, along with hands‑on experience developing or applying AI solutions for engineering workflows.

KEY RESPONSIBILITIES:

• Develop and maintain high-quality RTL in Verilog/SystemVerilog for ASIC/SoC products
• Participate in architecture definition, microarchitecture development, implementation, and integration
• Develop UVM-based verification environments, test plans, testcases, assertions, and coverage models
• Debug functional, performance, and integration issues across IP, subsystem, and SoC levels
• Develop AI agents and copilots to accelerate RTL design, verification, debug, code review, and productivity workflows
• Apply LLMs and Agentic AI technologies to automate tasks such as RTL understanding, test plan and assertion generation, coverage analysis, debug triage, and regression failure root‑cause analysis
• Build AI-powered engineering workflows using Python, LangChain, MCP, vector databases, and modern GenAI platforms
• Collaborate closely with Architecture, Design, DV, Physical Design, Emulation, Post‑Silicon, and Software teams to identify high‑impact AI use cases
• Drive AI adoption across silicon engineering teams; share best practices, methodologies, and reusable AI frameworks
• Mentor engineers on AI-assisted design and verification technologies, and measure/report productivity improvements enabled by AI solutions

REQUIREMENTS:

• 3+ years of experience in ASIC/SoC RTL Design and/or Design Verification
• 1+ year of practical experience applying AI/ML or Generative AI technologies
• Strong knowledge of Verilog/SystemVerilog and RTL design methodologies
• Experience with ASIC/SoC development flow, UVM verification, functional coverage, and assertions (SVA)
• Experience with Generative AI / LLMs, prompt engineering, and AI agent workflows
• Strong Python programming skills, with experience in Git, Linux, and scripting automation
• Familiarity with RAG architectures, MCP tools, and frameworks such as LangChain, LangGraph, AutoGen, or CrewAI
• Familiarity with cloud AI platforms and AI-assisted software development tools
• Experience with industry-standard EDA and simulation/debug tools is a plus