SoC/IP Design Verification Engineer

Intel Corporation; Región Centro; Presencial; MXN 1.048.951 - 1.748.252; Jornada completa

Descripción de la vacante

Intel Corporation is seeking a hands-on SoC Design Verification Engineer in Guadalajara, Jalisco. This role involves driving verification for complex SoC/IP blocks, focusing on verification planning, UVM testbench development, and collaborating with teams to ensure delivery of high-quality silicon.

The ideal candidate must have a Bachelor's degree in Electrical Engineering and over 5 years of experience in design verification. Responsibilities include owning verification lifecycles and debugging across various stages.

Formación

• 5+ years of experience in SoC/IP design verification.
• Expertise in UVM/SystemVerilog for testbenches and agents.
• Proven debug skills in simulation and emulation tools.

Responsabilidades

• Own the verification lifecycle for IPs and SoC features.
• Architect and implement UVM environments and test content.
• Debug failures across simulation and emulation.

Conocimientos

UVM/SystemVerilog development expertise

5+ years of experience in SoC/IP design verification

Debug skills in simulation/emulation

Scripting proficiency (Python, Shell)

Educación

Bachelor's degree in Electrical Engineering

Herramientas

Synopsys VCS

Cadence Xcelium

Siemens Questa

Descripción del empleo

Job Overview

This position requires candidates to upload a resume in English; multiple versions may be submitted, but at least one English version is required to be considered for this position. We are looking for a hands‑on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. The engineer will own verification planning, UVM testbench development, test content creation (directed and constrained‐random), coverage closure, and debug across block, subsystem, and SoC levels, collaborating closely with design, architecture, firmware, and validation teams to deliver high‑quality silicon on schedule.

Key Responsibilities

Own the verification lifecycle for one or more IPs/subsystems/SoC top‑level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff.

Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reusable components.

Develop test content: constrained‑random sequences, scenario tests, stimulus libraries, checkers, and assertions.

Debug failures quickly and methodically across simulation and emulation (waveforms, logs, assertions, checkers, reference model mismatches).

Drive coverage closure (functional and code coverage): define, measure, analyze holes, and implement closure strategies.

Leverage assertions (SVA) and formal where appropriate to strengthen verification quality and accelerate bug find.

Integrate VIPs (e.g., AXI/ACE/PCIe/DDR) and coordinate with external/internal IP teams for models, checkers, and coverage.

Collaborate cross‑functionally with RTL design, architecture, DV, DFT, performance, firmware, and post‑silicon validation to ensure feature completeness and testability.

Continuously improve flows: contribute to methodology, regressions, CI/CD, and verification infrastructure (e.g., Makefiles, Python utilities, farm scripts).

Document plans, environments, and results; present status, risks, and signoff evidence to stakeholders.

Behavioral Traits

Problem‑Solving Mindset: Approaches complex technical challenges with curiosity, creativity, and structured analytical thinking.

Collaboration Skills: Works effectively with cross‑functional engineering teams, seeks input from partners, and communicates clearly in both technical and non‑technical contexts.

Adaptability and Learning Agility: Quickly learns new tools, technologies, and methodologies; comfortable working in evolving development environments.

Attention to Detail: Delivers high‑quality, reliable, and scalable software solutions with a focus on robustness, validation, and secure coding practices.

Results‑Oriented: Prioritizes effectively, manages time well, and drives solutions to completion in a fast‑paced engineering environment.

Innovation and Continuous Improvement: Looks for opportunities to optimize tools, simplify workflows, and introduce new methodologies that enhance engineering efficiency.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in SoC/IP design verification.
• UVM/SystemVerilog development expertise (testbenches, agents, scoreboards, virtual sequences, factory/objection/callback mechanisms).
• Test planning experience: translating architectural/RTL specs into measurable, coverage‑driven verification plans.
• Proven debug skills in simulation/emulation (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools like Verdi/DVE/SimVision).
• Coverage‑driven verification: functional coverage modeling, code coverage analysis, coverage closure workflows.
• Scripting proficiency (Python, Shell, Make/CMake) for automation, regressions, and data analysis.
• Advance English level.
• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications

• SoC‑level verification experience: fabric/interconnect, security.
• Experience with standard protocols: AXI/ACE/CHI, PCIe, LP/DDR, USB, MIPI, I3C, SPI/I2C, Ethernet; integrating and customizing VIP.
• Assertion‑based verification (SVA) and formal (JasperGold/VC Formal/PropCheck) for property checking and bug hunting.
• Power‑aware verification (UPF/CPF), isolation/retention, multi‑voltage domains.
• Emulation/FPGA prototyping (Palladium, Zebu, Veloce), transaction‑level acceleration, hybrid verification.
• Performance/latency/throughput test content and checkers; scoreboard/reference model design for complex data paths.
• Exposure to C/C++/SystemC reference models or firmware‑aware verification.
• Experience leading small teams, mentoring, or driving signoff for a tapeout.

Job Type and Location

Job Type: Experienced Hire

Shift: Shift 1 (Mexico)

Primary Location: Mexico, Guadalajara

Posting Statement (EEO)

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.