Senior SoC Verification Engineer: UVM, Coverage & Debug

Intel; Región Centro; Presencial; MXN 700.000 - 1.100.000; Jornada completa

Descripción de la vacante

Intel in Mexico is seeking a hands-on SoC Design Verification Engineer to drive verification for complex IP blocks and SoC features. You will own planning, UVM testbenches, constrained-random testing, coverage closure, and debug across levels, collaborating with design, architecture, firmware, and validation teams to deliver silicon on schedule.

Minimum qualifications include a bachelor's in Electrical or Computer Engineering and 5+ years in SoC/IP verification, with strong UVM/SystemVerilog,

Formación

• Bachelor's degree in Electrical Engineering or Computer Engineering.
• 5+ years of SoC/IP design verification experience.
• UVM/SystemVerilog development for testbenches, agents, scoreboards and sequences.
• Proven debug skills in simulation and emulation (waveforms/logs).
• Coverage-driven verification: functional and code coverage; closure workflows.
• Scripting proficiency (Python, Shell, Make/CMake) for automation and data analysis.
• Advanced English level.

Responsabilidades

• Own the verification lifecycle for IPs/subsystems/SoC features: requirements, test plan, coverage strategy, execution, signoff.
• Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards).
• Develop constrained-random test content, scenario tests, checkers, and assertions.
• Debug failures across simulation and emulation (waveforms, logs, reference models).
• Drive coverage closure and signoff, analyze holes, implement strategies.
• Leverage SVA and formal methods for property checking.
• Integrate VIPs (AXI/ACE/PCIe/DDR) and collaborate with IP teams.
• Collaborate with RTL, architecture, DV, firmware, and post-silicon validation.
• Contribute to CI/CD, regression tooling, and verification infrastructure.
• Document plans, environments, and results; present risks and status.

Conocimientos

SoC/IP verification

UVM/SystemVerilog

Test planning

Debugging

Scripting (Python)

English proficiency

Educación

Bachelor's degree in Electrical or Computer Engineering

Herramientas

Synopsys VCS

Cadence Xcelium

Siemens Questa

Verdi/DVE/SimVision

JasperGold/VC Formal

Descripción del empleo

Intel in Mexico is seeking a hands-on SoC Design Verification Engineer to drive verification for complex IP blocks and SoC features. You will own planning, UVM testbenches, constrained-random testing, coverage closure, and debug across levels, collaborating with design, architecture, firmware, and validation teams to deliver silicon on schedule.

Minimum qualifications include a bachelor's in Electrical or Computer Engineering and 5+ years in SoC/IP verification, with strong UVM/SystemVerilog,