SoC Synthesis & PPA Optimization Engineer

North American Production Sharing, Inc.; Tijuana; Presencial; MXN 600.000 - 900.000; Jornada completa

Descripción de la vacante

North American Production Sharing, Inc. seeks an ASIC design engineer to synthesize large-scale SoC RTL into gate-level netlists and own multi-stage synthesis flows, ensuring PD handoff readiness.

You will optimize PPA, analyze timing constraints (SDC), and support functional ECOs while collaborating with Design, DFT, and Physical Design teams to deliver robust, manufacturable Snapdragon-class designs. Frontend experience in ASIC design and strong debugging, scripting, and execution under tight

Formación

• Bachelor's degree in Science, Engineering, or related field; 2+ years ASIC design experience.
• Master's degree or PhD with related ASIC design/verification experience.
• Experience with gate-level netlist quality checks and PD-ready handoffs.
• Strong knowledge of timing constraints (SDC) across functional and test modes.
• Ability to analyze and optimize PPA trade-offs.
• Experience supporting functional ECOs and validating correctness.
• Excellent debugging and analytical thinking under tight project schedules.

Responsabilidades

• Own synthesis inputs and execute multi-stage synthesis flows.
• Ensure netlist quality with respect to timing, power, and DFT before PD handoff.
• Contribute to PPA optimization by analyzing trade-offs and recommending improvements.
• Work with Design, DFT, and Physical Design teams to resolve issues early in the flow.
• Support functional ECOs and validate post-change correctness.
• Document IP development and enable robust, manufacturable designs.

Conocimientos

gate-level netlist checks

PD-ready handoffs

timing constraints (SDC)

PPA optimization

functional ECOs

debugging & analysis

synthesis flow execution

tight schedules

ASIC design experience

scripting languages

Educación

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Herramientas

RTL to GDS Flow

Virtuoso

Python scripting

EDA tools

Spice simulations

Descripción del empleo

North American Production Sharing, Inc. seeks an ASIC design engineer to synthesize large-scale SoC RTL into gate-level netlists and own multi-stage synthesis flows, ensuring PD handoff readiness.

You will optimize PPA, analyze timing constraints (SDC), and support functional ECOs while collaborating with Design, DFT, and Physical Design teams to deliver robust, manufacturable Snapdragon-class designs. Frontend experience in ASIC design and strong debugging, scripting, and execution under tight