SoC Design & Synthesis Engineer

Qualcomm; Tijuana; Presencial; MXN 1.223.989 - 1.661.129; Jornada completa

Descripción de la vacante

Qualcomm is seeking a SoC Design & Synthesis Engineer in Tijuana, Baja California. This role is essential for synthesizing large-scale SoC RTL designs into high-quality gate-level netlists, ensuring design efficiency across multiple platforms such as mobile and automotive.

Ideal candidates should have robust experience in ASIC design, with an emphasis on RTL-to-gate synthesis, timing constraints, and optimization techniques. The job offers a dynamic environment where you'll collaborate with various teams to deliver high-performance products.

Formación

• 2+ years of ASIC design or related experience with a Bachelor's degree.
• 1+ year experience with a Master's degree in related field.
• PhD in Science, Engineering, or related field.

Responsabilidades

• Synthesize large-scale SoC RTL designs into gate-level netlists.
• Optimize PPA by analyzing trade-offs.
• Support functional ECOs and validate designs.

Conocimientos

RTL-to-gate synthesis

Gate-level netlist quality checks

Timing constraints knowledge

PPA optimization

Functional ECOs experience

Analytical thinking

Educación

Bachelor's degree in Science, Engineering or related field

Master’s or PhD in related field

Herramientas

EDA tools

Architecture/design tools

Scripting tools

Descripción del empleo

Company

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

SoC Design & Synthesis Engineer

Role Description

This role focuses on synthesizing large‑scale SoC RTL designs into high‑quality gate‑level netlists that are ready for Place & Route. Responsibilities include owning all synthesis inputs, executing multi‑stage synthesis flows, and ensuring netlist quality with respect to timing, power, and DFT requirements prior to Physical Design handoff.

The role also contributes to PPA (Power, Performance, Area) optimization by analyzing trade‑offs and recommending design or constraint improvements, while working closely with Design, DFT, and Physical Design teams to resolve issues early in the flow. In addition, the engineer supports functional ECOs and validates post‑change correctness to improve functionality and fix late‑stage issues, ensuring timely delivery of robust, manufacturable designs used in Snapdragon products across mobile, automotive, and edge AI platforms.

Required Skills

• Strong understanding of RTL‑to‑gate synthesis for large SoC designs


• Experience with gate‑level netlist quality checks and PD‑ready handoffs


• Solid knowledge of timing constraints (SDC) across functional and test modes


• Ability to analyze and optimize PPA (Power, Performance, Area) trade‑offs


• Experience supporting or implementing functional ECOs and validating correctness


• Effective debugging, analytical thinking, and execution under tight project schedules

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.


• OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.


• OR PhD in Science, Engineering, or related field.

Preferred Qualifications

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.


• 3+ years of ASIC design, verification, validation, integration, or related work experience.


• 2+ years of experience with architecture and design tools.


• 2+ years of experience with scripting tools and programming languages.


• 2+ years of experience with design verification methods.

Principal Duties & Responsibilities

• Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.


• Creates architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements.


• Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.


• Evaluates all aspects of process flow from high‑level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.


• Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.


• Writes detailed technical documentation for EDA/IP/ASIC projects.

Level of Responsibility

• Works independently with minimal supervision.


• Decision‑making may affect work beyond immediate work group.


• Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.


• Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).


• Tasks require multiple steps which can be performed in various orders; some planning, problem‑solving, and prioritization must occur to complete the tasks effectively.

EEO Statement

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.